Signal integrity analysis of bundled carbon nanotubes as futuristic on-chip interconnects

Pathade, Takshashila; Agrawal, Yash; Parekh, Rutu; Palaparthy, Vinay S.

doi:10.1016/j.matpr.2020.12.1182

Cited by 2 publications

(1 citation statement)

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“…On the other hand, the crosstalk delay occurs when the aggressor lines switch simultaneously with the victim line, increasing the delay of logic paths. 20 The second effect is entirely more critical in on-chip buses, where the adjacent bus lines may switch simultaneously by the active clock edge, and an enormous additional crosstalk delay can lead to setup time violation and logic failure.…”

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confidence: 99%

An Energy-Efficient Crosstalk Reduction Strategy for On-Chip Buses Using Carbon-Based Transistors and Interconnects

Azimi

Moaiyeri

Hamedani

2021

ECS J. Solid State Sci. Technol.

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This paper presents a novel crosstalk reduction scheme based on quaternary logic that eliminates the harmful transition patterns and protects communication channels of system-on-chips (SoCs) against crosstalk. The proposed architecture is designed based on gate-all-around carbon nanotube field-effect transistor (GAA-CNTFET) codec and converter modules considering multi-walled carbon nanotube (MWCNT), and multilayer graphene nanoribbon (MLGNR) interconnects at 10 nm technology. The simulation results indicate that our proposed approach reduces the delay and power-delay product (PDP) on average by 52% and 36%, respectively, for MWCNT interconnects compared to the basic architecture. These improvements are 50% and 35% for the MLGNR interconnects. Moreover, utilizing the MLGNR interconnects instead of MWCNT interconnects in the proposed coded system leads to a 61% shorter crosstalk delay and 65% lower PDP. In addition, the proposed coding scheme leads to 35% reduction in the occupied area and improves PDP, on average, by 37%, and 26% for the MWCNT and MLGNR buses, respectively, as compared to their binary counterparts.

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confidence: 99%