Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions

Fan, Jun; Ye, Xiaoning; Kim, Jingook; Archambeault, Bruce; Orlandi, Antonio

doi:10.1109/temc.2010.2045381

Cited by 245 publications

(63 citation statements)

References 56 publications

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“…Figure 3 shows the signal in the PCB or cable poor data rate trends, such as serial advanced technology attachment, peripheral component interconnect Express (PCIe), universal serial bus, projection is 20 Gbps in the next ten years. Typically, a differential (or balanced) line is composed of three conductors (two signal conductors and one ground conductor) that support two fundamental modes, differential (or odd) mode and common (or even) mode [2]. In the differential signal system, common mode signal is usually regarded as noise, thereby reducing the signal integrity and electromagnetic interference problem caused by.…”

Section: The Eye Diagram Examplementioning

confidence: 99%

“…In order to account for uncertainties affecting the wave propagation along distributed transmission lines, we refer to the theory of telegraph equations, to which Clayton Paul significantly contributed and rigorously and elegantly described in [2]. The transmission line governing equations in the Laplace domain:…”

Section: Mathematical Analysis and Modelingmentioning

confidence: 99%

“…Clayton Paul a few EMC and SI field has made a pioneering contribution. He condensed the basic theory and requires knowledge of the EMC and SI two masterpiece design book [1], [2]; and then, in more recent times, he published a series of more books [3], especially the design of high speed digital system. This information not only guided electromagnetic compatibility and PCB in the past few decades, some new techniques of silicon research direction and inspiration, but at present still unmatched, many years of electronic systems development influence.…”

Section: Introductionmentioning

confidence: 99%

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Research on High-speed PCB Design Based on Signal Integrity Analysis

Zhao¹

2015

Advances in Intelligent Systems Research

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Abstract. With the development of manufacturing techniques and hardware devices, the need for high-speed chips is bursting. As a review report, we analyze the fundamentals and latest progress of modeling, analysis, and design technologies for signal integrity and electromagnetic compatibility on PCB and package in the past decades. Most results in this area are very rich and highly education during his long scientific career based on Professor Clayton Paul's literary creation also consider the inclusion variability of parameters, it is shown how statistical simulation can be affordable by the recently introduced stochastic method. As the final conclusion, we take into consideration of the necessity of practical training of designers and an experience relying on realistic PCB demonstrators is illustrated and discussed.

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Section: The Eye Diagram Examplementioning

confidence: 99%

Section: Mathematical Analysis and Modelingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Research on High-speed PCB Design Based on Signal Integrity Analysis

Zhao¹

2015

Advances in Intelligent Systems Research

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“…Conventional high-speed digital circuits transmit signals by differential signaling [1]. Common applications include Serial Advanced Technology Attachment III (SATA III/6 Gbps), High Definition Multimedia Interface (HDMI/5 Gbps), PCI Express Interconnect III (8 Gbps), and USB 3.0 (5 Gbps) devices.…”

Section: Introductionmentioning

confidence: 99%

“…The advantages of using differential signals include improved signal integrity (SI), cancellation of electromagnetic interference (EMI), and immunity to noise [2]. However, an imbalance between differential signals and common mode noise (CMN) can worsen EMI problems by generating common mode current radiation that is transmitted through I/O cables [1,3]. Therefore, a maximum common-mode voltage must be specified for high-speed GHz differential transmission systems such as USB 3.0.…”

Section: Introductionmentioning

confidence: 99%

Generation and Mitigation of Common-Mode Noise for Differential Traces With Adjacent Ground Line and Ground Plane

Shiue¹,

You²,

Cheng³

et al. 2017

PIER M

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Abstract-This study investigates the generation and mitigation of common-mode noise (CMN) in a common structure which consists of differential traces with adjacent ground lines and a ground plane. For simplicity, a simple test structure similar to the common structure is proposed. The test structure is divided into three parts. One part is composed of differential traces with adjacent ground lines. The second is composed of differential traces with adjacent ground lines that are connected to a ground plane. The third comprises differential traces with an adjacent ground line and an adjacent ground plane. The generation and mitigation of CMN in these three parts are studied. Test structures with different designs are investigated to confirm the effectiveness of the CMN mitigation schemes. Based on these analyses, design guidelines for mitigating CMN are provided. The proposed design guidelines reduce the peak-to-peak CMN amplitude by 81% from that achieved using unsuitable design of test structure. In the frequency domain, the reduction of the magnitude of differential-to-common mode conversion (|S cd21 |) at the resonant peaks exceeded 40 dB in the frequency range 0 GHz ∼ 6 GHz. Finally, a comparison between simulated and measured results verifies the favorable CMN mitigation performance of the proposed design guidelines.

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Theory on asymmetrical coupled‐parallel‐line transmission and reflection zeros

Ravelo

2017

Circuit Theory & Apps

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Summary This paper treats an innovative methodology on the synthesis mechanism of the coupled‐parallel‐line (CPL) transmission zero (TZ) and reflection zero (RZ). The CPL structure under study is configured as a reflection type distributed arbitrarily loaded stub circuits. On the basis of the equivalent Z‐matrix analysis, the CPL input impedance theoretical model is established. Mathematical analysis is performed to predict accurately the TZ and RZ frequency shifts in function of the CPL physical parameters. The input impedance behavioral model in function of asymmetrical CPL load parameters is determined. The TZ and RZ existence conditions are established. Then, the characteristic equations illustrating the TZ and RZ fundamental formulas in function of the CPL coupling coefficient and characteristic impedances are examined. Furthermore, innovative graphical representations of the TZ and RZ existence conditions in function of the CPL parameter ranges are explored. The developed CPL model was validated with different cases of simulated microstrip proof of concept. As expected, a good correlation between the TZ and RZ frequency shifts from the analytical calculations and simulations is obtained. The developed CPL model is useful for the TZ and RZ frequency shifts fast monitoring during the Radio Frequency (RF)/microwave circuit design phase. Copyright © 2017 John Wiley & Sons, Ltd.

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Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions

Cited by 245 publications

References 56 publications

Research on High-speed PCB Design Based on Signal Integrity Analysis

Research on High-speed PCB Design Based on Signal Integrity Analysis

Generation and Mitigation of Common-Mode Noise for Differential Traces With Adjacent Ground Line and Ground Plane

Theory on asymmetrical coupled‐parallel‐line transmission and reflection zeros

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