Signal Integrity Impact of Ultra Low Power IO Initiatives

Abstract

C05-177, (stevenyun.jiintellcom) Steve Peterson, FM7-287, steven.peterson@intel.com) Jian-Liang Chen, C05-177, (/ian-1iang.chen@intel,com) Christopher Pan, C05-1577,,herpanintel.com ABSTRACT I/O power represents a sizeable portion of the overall power budget on a low power mobile platform. Significant fraction of that I/O power is used to ensure signal integrity on the high speed buses. While there is flexibility to trade off I/O power consumption against signal quality on Intel's current mobile and sub-note platforms, inefficiency still exists on wide I/O buses such as FSB and DDR2. In this paper, we will outline two novel bus termination schemes that can significantly reduce FSB and DDR2 I/O power consumption by further trading off signal quality on the new Low Power IA (LPIA) Ultra Small PC (UMPC) platforms.

Novel bus termination schemes to reduce IO power consumption on low power intel small form factor platforms

“…Overshoot/undershoot (OS/US) and voltage/timing margin violations are some of the many signal quality issues in conventional mobile platforms, because of the complex routing topologies and longer lengths. Terminating IO pads on motherboards or silicon help improve these violations, but they also result in significant power dissipation through DC paths from the pads to supply and ground [1].…”

Package to board interconnect design for minimum return loss

“…Therefore, in compact devices, return loss and crosstalk are playing a more important role on signal integrity. In addition, in these ultra-low power systems the IO power represents a considerable portion of the total power budget [1]; therefore, it is very important to design physical channels with the smallest possible impedance discontinuities. One important source of signal reflection is the discontinuity introduced by the combination of package vias and solder balls existing in package to board transitions.…”