Signed power-of-two term allocation scheme for the design of digital filters

Lim, Yong Ching; Yang, Rui; Li, Dongning; Song, Jianjian

doi:10.1109/82.769806

Cited by 123 publications

(7 citation statements)

References 13 publications

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“…For each employed bee determine a new food source within the neighbourhood of the food source in their memory. The new food source is produced by (9).…”

Section: Employed Bee Phasementioning

confidence: 99%

“…If it is possible to represent the multiplication coefficients as SPT terms, then the multiplier circuits can be implemented by using shifters and adders/subtraction circuits. CSD representation is an encoding where a binary number contains the fewest number of nonzero bits [9]. The number of partial product addition and hence adders are determined by the total number of non zero bits in the filter coefficient representation.…”

Section: Canonic Signed Digit Representationmentioning

confidence: 99%

“…This is achieved by converting the maximum precision filter coefficients into finite precision coefficients using signed power of two (SPT) systems. The SPT system allows the multiplications to be replaced by shift and add operations [9], which reduces circuit complexity. Hence low power hardware realization is possible, because the multipliers are the major power and silicon area consuming components in the physical realizations of filters.…”

Section: Introductionmentioning

confidence: 99%

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Design of Multiplier-less Continuously Variable Bandwidth Sharp FIR Filters using Modified Gravitational Search Algorithm

James¹,

Elias²

2013

IJCA

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Variable Bandwidth Filters (VBFs) find applications in software defined radios, trans-multiplexers etc. The key features essential for fractional changes in the bandwidth of a VBF are low complexity, easy re-configurability and fine tuning capability. A VBF which has the capability to reduce the bandwidth has been reported recently. This paper proposes the design of a multiplier-less, sharp VBF based on FRM. It is capable of both bandwidth reduction and enhancement. To make the filter totally multiplier-less, the filter coefficients are synthesized in the Canonic Signed Digit (CSD) format. This is formulated as an optimization problem. Recently, Artificial Bee Colony (ABC) algorithm has been proposed for the discrete optimization of the FRM filter performance. In this paper, Gravitational Search Algorithm (GSA) is deployed to get the optimized filter coefficient values.

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“…For each employed bee determine a new food source within the neighbourhood of the food source in their memory. The new food source is produced by (9).…”

Section: Employed Bee Phasementioning

confidence: 99%

Section: Canonic Signed Digit Representationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design of Multiplier-less Continuously Variable Bandwidth Sharp FIR Filters using Modified Gravitational Search Algorithm

James¹,

Elias²

2013

IJCA

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“…So the number of adders can be reduced by reducing the number of non-zero bits in the filter coefficients. CSD representation is a unique representation of the filter coefficients with minimum number of non-zero bits [10]- [11]. A fractional number q is represented in CSD format as [11].…”

Section: Canonic Signed Digit Representation (Csd)mentioning

confidence: 99%

“…This is achieved by converting the infinite precision filter coefficients into finite precision coefficients using signed power-oftwo (SPT) space. The SPT system allows the multiplications to be replaced by shift and add operations [10]. Since the multipliers are the major power and area consuming components of a filter, this results in low power hardware realizable digital filters.…”

Section: Introductionmentioning

confidence: 99%

Design of Multiplier-less Reconfigurable Non-uniform Channel Filters using Meta-heuristic Algorithms

Bindiya¹,

Elias²

2012

IJCA

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Low complexity and reconfigurability are reported to be the key features in a software defined radio (SDR). To obtain these features, a reconfigurable architecture based on frequency response masking (FRM) technique can be used for the implementation of the channel filters in the SDR. The frequency response masking approach is proved to be a good candidate for the realization of a sharp digital finite impulse response (FIR) filter with low complexity. To reduce the complexity and power consumption for hardware realization, a design method which makes the channel filters totally multiplierless is proposed in this paper. Continuous filter coefficients are first converted to finite precision coefficients using signed power of two (SPT) space to obtain a multiplier-less filter. The representation of the FRM filter coefficients in the SPT space can degrade the filter performance. This calls for the use of a suitable optimization technique. The classical gradient based optimization techniques cannot be deployed here, because the search space consists of integers. In this context, meta-heuristic algorithm is a good choice as it can be tailor made to suit the problem under consideration. They are especially useful in finding near optimal solutions in multimodal, multidimensional space. Several meta-heuristic algorithms are modified in this paper to be used for the discrete optimization.

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