Significance-Aware Program Execution on Unreliable Hardware

Abstract

This article introduces a significance-centric programming model and runtime support that sets the supply voltage in a multicore CPU to sub-nominal values to reduce the energy footprint and provide mechanisms to control output quality. The developers specify the significance of application tasks respecting their contribution to the output quality and provide check and repair functions for handling faults. On a multicore system, we evaluate five benchmarks using an energy model that quantifies the energy reduction. When executing the least-significant tasks unreliably, our approach leads to 20% CPU energy reduction with respect to a reliable execution and has minimal quality degradation.

Optimization of program execution using computational significance

“…All inputs need to be registered before the first intermediate user variable, intermediate user variables need to be registered straight after their computation, and output variables last. Moreover, for a vector valued function y = F ( x) with F : This section discusses the models we use for unreliable execution which were introduced in [71]. We discuss how we combine simulation-based and software-based fault injection to map the fault rates derived from the model into actual errors at the application level.…”

“…We use an analytical model for the performance and energy consumption of a program that is implemented in a task-based fashion. We generate the analytical model as a function of the core frequency, the voltage, the number of tasks that are executed reliably and unreliably and the number of voltage and frequency transitions that was introduced in [71]. The model is agnostic to the CPU structure and captures the execution phases of an application.…”

“…We evaluate the efficiency of ANNs acting as error detectors using the framework described in [71]. The runtime system executes the main application thread under reliable conditions and schedules tasks on 4 worker threads which are mapped on the cores of an Intel i7 4820k CPU.…”

“…We resort to software fault injection to simulate the unreliable execution of code using the methodology described in [71]. A fault-injection experiment injects random, multiple bit-flip faults on CPU registers once every 10 7 cycles.…”

“…The results presented in this Thesis have been partially published in [100,71,102,101,99,98]. This appendix discusses my contribution to each of the aforementioned publications.…”