Significant Off-State Leakage Reduction for n-FinFET by Self-Adaptive TiN Etching

Huang, Tao; Cai, Han-Lun; He, Song; Li, Zhao-Yang; Jiang, Yu-Long

doi:10.1109/ted.2023.3304603

Cited by 1 publication

(1 citation statement)

References 17 publications

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“…In recent decades, multi-gate devices have been considered the most promising devices for advanced nodes at 22 nm and beyond, with significant improvements in short-channel effects (SCEs) [1]. Compared to traditional planar MOSFETs, FinFETs exhibit higher driving capability and superior gate control ability, leading to their successful development for highvolume integrated circuits from the 22 nm to 5 nm nodes [2,3].…”

Section: Introductionmentioning

confidence: 99%

Leakage and Thermal Reliability Optimization of Stacked Nanosheet Field-Effect Transistors with SiC Layers

Li,

Shao,

Kuang

et al. 2024

Micromachines

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In this work, we propose a SiC-NSFET structure that uses a PTS scheme only under the gate, with SiC layers under the source and drain, to improve the leakage current and thermal reliability. Punch-through stopper (PTS) doping is widely used to suppress the leakage current, but aggressively high PTS doping will cause additional band-to-band (BTBT) current. Therefore, the bottom oxide isolation nanosheet field-effect transistor (BOX-NSFET) can further reduce the leakage current and become an alternative to conventional structures with PTS. However, thermal reliability issues, like bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB), induced by the self-heating effect (SHE) of BOX-NSFET, become more profound due to the lower thermal conductivity of SiO2 than silicon. Moreover, the bottom oxide will reduce the stress along the channel due to the challenges associated with growing high-quality SiGe material on SiO2. Therefore, this method faces difficulties in enhancing the mobility of p-type devices. The comprehensive TCAD simulation results show that SiC-NSFET significantly suppresses the substrate leakage current compared to the conventional structure with PTS. In addition, compared to the BOX-NSFET, the stress reduction caused by the bottom oxide is avoided, and the SHE is mitigated. This work provides significant design guidelines for leakage and thermal reliability optimization of next-generation advanced nodes.

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Section: Introductionmentioning

confidence: 99%