Silicides for integrated circuits: TiSi2 CoSi2

Interfacial reactions of Ti/ and Zr/Si1−xGex/Si contacts with rapid thermal annealing

“…The lattice spacing estimated by the diffraction peak from the (131) plane is larger by about one percent than that in Ti/Si systems. In the case of Ti/Ge systems, C49-TiGe 2 is not a stable phase, because the first phase formed by annealing at low temperatures is not C49-TiGe 2 but Ti 6 Ge 5 and that Ti 6 Ge 5 is transformed to C54-TiGe 2 at high temperatures [9,14,15]. However, the estimated lattice spacing suggests that Ge atoms are contained in C49-TiSi 2 crystallites in Ti/Si 0.5 Ge 0.5 systems.…”

Texture in thin film silicides and germanides: A review

“…17 This silicide was used until linewidths in devices reached 50 nm and several issues with CoSi 2 formation in these narrow lines arose:…”

“…Eventually, the industry settled on the use of TiSi 2 in the early 1990s, but issues with the nucleation of the low-resistive C54-TiSi 2 within the initially formed high-resistive C49-TiSi 2 phase in lines narrower than 250 nm forced a change to CoSi 2 . 17 When feature sizes eventually reached sub 50 nm dimensions, CoSi 2 started showing severe voiding issues in these narrow lines which led to the introduction of NiSi. 18 In modern planar CMOS technology, NiSi modified by the addition of a small amount of Pt still is the contacting material of choice.…”

Quantitative Evaluation of Cobalt Disilicide/Si Interfacial Roughness

“…[2][3][4] CoSi 2 has been used for various electronic devices, such as memory electrode for 3D structure 5 and the metallization material for nanoparticles, nanowires 6,7 . As devices scale down, a thin, uniform CoSi 2 layer is essential for those nano-electronic applications.…”

“…2 However, the conventional sputtering process results in poor step coverage and induces high ion damage in the active regions, making it undesirable for complex 3D…”