Silicon‐Based Devices and Materials for Nanoscale CMOS and Beyond‐CMOS

Abstract

At the end of the ITRS, new materials, nanotechnologies and device architectures will be needed for nanoscale CMOS and beyond-CMOS. Silicon-on-insulator (SOI)-based devices are promising for the ultimate integration of electronic circuits on silicon [1]. We will discuss a number of key issues, including: the performance of single-and multi-gate thin film MOSFETs; the comparison between Si, Ge and III-V SOI channels; the effects of strain, high-κ materials, and Schottky source-drain (S/D) contacts. We then proceed to beyond-CMOS nanodevices based on nanowires or tunnel FETs and, finally, to an overview of advanced memory architectures on the nanoscale.Strained SOI is very interesting for boosting performance, with electron and mobilities enhanced by uniaxial tensile and compressive strains respectively, down to ultrathin channels [2]. Schottky S/D engineering is also promising for nanoscale CMOS, with PtSi/Si contacts producing record current drive and RF performance in p-channel SOI MOSFETs [3]. In the high-κ arena, the product of κ and the energy barrier that determines the gate leakage current can be set lower for double-gate (DG) SOI than bulk CMOS, offering a wider choice of gate dielectrics [4]. Multi-gate architectures based on volume inversion are expected to provide higher current drive down to sub-10nm gate lengths [5]. Further out, multi-bridge-channel MOSFETs [6] and gate-all-around SOI nanowires with tunable thresholds [7] represent the ultimate integration of innovative nanodevices with promising electrical properties.In the advanced memory arena, we will discuss capacitorless one-transistor DRAMs [8] and various variants of FinFlash memories that offer good downscaling prospects [9]. Independent DG FinFETs are also candidates for enhanced SRAM performance due to lower leakage and better noise margins [10]. Finally, there are promising tunneling FET candidates that may provide sharp switching for beyond-CMOS low-power applications, including DG high-κ TFETs, strain Ge DG with asymmetric source/drain and feedback TFETs [11][12][13].

Ultralow-Power Device Operation

“…A buried insulator, which is typically an oxide layer, is fabricated in the silicon substrate using various methods. A number of advantages, suitable for many applications, are obtained with the SOI structure, which allows us to push back the technological and physical limits intrinsic to the bulk Si structure [6,7]:…”

Analytical Drain Current Model of 1-D Ballistic Schottky-Barrier Transistors

“…For short-channel devices at a small gate voltage V gs in the subthreshold region, the thermionic current approximation is not adequate because of a direct source-to-drain tunneling [30], [32], [51]. For the sake of simplicity, we develop a semiempirical model in this case.…”

Theoretical investigation of the phonon-limited carrier mobility in (001) Si films

“…7,13 As a matter of fact, N e ac % 12 eV is often used in simulations on bulk MOSFETs. 55,75 An even higher value N e ac ¼ 14.6 eV is widely used in simulations on FDSOI and Si nanowire FETs, 6,13,48,76,77 which corresponds to an increase of roughly 50% with respect to the bulk. To solve this issue, other authors have introduced a spatially dependent N e ac , which sharply increases close to the interfaces with the oxide.…”