Conference Record of the 2001 IEEE Industry Applications Conference. 36th IAS Annual Meeting (Cat. No.01CH37248)
DOI: 10.1109/ias.2001.955443
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Silicon carbide GTOs: static and dynamic characterization

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Cited by 4 publications
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“…Therefore, the SM-JTE and ESZ-JTE designs are benchmarked in the following section. It should be kept in mind that the SiC material quality has evolved significantly during the last decades, as the chip size, drift thickness and blocking capability have increased from 1x1mm 2 , 12 µm, and 3 kV, respectively, in 2001 [51], 10x20 mm 2 , 160 µm and 20 kV, respectively, in 2013 [20], to 3.5x3.5 mm 2 , 230 µm and 26.8 kV, respectively, in 2020 [8]. The development of epitaxial growth methods has enabled high growth speeds (i.e., > 100 µm/h [52]) and with low levels of critical traps and dislocations (i.e., deep-level trap density < 1×10 11 cm -3 [52]).…”
Section: B Single-zone Negative-bevel Jte and Single-zone Etched-step Jte Designs For Ultrahigh-voltage Devicesmentioning
confidence: 99%
“…Therefore, the SM-JTE and ESZ-JTE designs are benchmarked in the following section. It should be kept in mind that the SiC material quality has evolved significantly during the last decades, as the chip size, drift thickness and blocking capability have increased from 1x1mm 2 , 12 µm, and 3 kV, respectively, in 2001 [51], 10x20 mm 2 , 160 µm and 20 kV, respectively, in 2013 [20], to 3.5x3.5 mm 2 , 230 µm and 26.8 kV, respectively, in 2020 [8]. The development of epitaxial growth methods has enabled high growth speeds (i.e., > 100 µm/h [52]) and with low levels of critical traps and dislocations (i.e., deep-level trap density < 1×10 11 cm -3 [52]).…”
Section: B Single-zone Negative-bevel Jte and Single-zone Etched-step Jte Designs For Ultrahigh-voltage Devicesmentioning
confidence: 99%