Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling

Peng, Yarui; Song, Taigon; Petranovic, Dusan; Lim, Sung Kyu

doi:10.1109/tcad.2014.2359578

Cited by 33 publications

(7 citation statements)

References 25 publications

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“…Since the capacitances of the C matrix are heterogeneous [5,10], the assignment of the logical bits to the TSVs affects the power consumption. Moreover, a fixed inversion of some of the logical bits before the transmission may potentially decrease the T entries.…”

Section: Preliminaries: Tsv Modelmentioning

confidence: 99%

“…metal-wire pair has the same size. In contrast, TSVs have a maximum of eight adjacent neighbors and due to the different distances between direct and diagonal adjacent neighbors, combined with the E-field sharing effect [10], several capacitance values exist in a TSV array [5]. Hence, traditional low-power coding techniques are not directly applicable for TSV arrays.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Coding Approach for Low-Power 3D Interconnects

Bamberg¹,

Schmidt²,

García-Ortiz³

2018

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

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Through-silicon vias (TSVs) in 3D ICs show a significant power consumption, which can be reduced using coding techniques. This work presents an approach which reduces the TSV power consumption by a signal-aware bit assignment which includes inversions to exploit the MOS effect. The approach causes no overhead and results in a guaranteed reduction of the overall power consumption. An analysis of our technique shows a reduction in the TSV power consumption by up to 48 % for real correlated data streams (e.g. image sensor), and 11 % for low-power encoded random data streams.

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Section: Preliminaries: Tsv Modelmentioning

confidence: 99%

mentioning

confidence: 99%

Coding Approach for Low-Power 3D Interconnects

Bamberg¹,

Schmidt²,

García-Ortiz³

2018

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

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show abstract

“…3-D ICs are becoming a good solution to continue Moore's law. TSV is a popular choice to implement the vertical connections between dies in 3-D ICs [2]. 3-D ICs has shorter global interconnect due to the short length of TSV and the flexibility of vertical routing, leading to higher performance and lower power consumption of interconnects [3].…”

Section: Introductionmentioning

confidence: 99%

Electrical analysis of TSV step change in radius with compensation structure

Zheng

Dong

Yang

et al. 2015

IEICE Electron. Express

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Through silicon via (TSV) is a key technology in 3-D integrated circuits (3-D ICs). At the junction of TSV and pad, an extra loss produced by the discontinuous structure is inevitable in microwave circuit, and it can not be ignored. A compensation structure which can compensate the loss from step change in radius is proposed in this paper. The conventional structure and compensation structure are simulated by High Frequency Structure Simulator (HFSS). Simulation result shows that the proposed compensation structure can effectively reduce the return loss within the whole frequency range, and the compensation of insertion loss is more obvious at higher frequency. A series of top layer compensation structures with different diameter ratios are simulated. The simulation result shows that the larger the diameter ratio, the more obvious the compensation is. As the analysis based on the impedance model of TSV correlates well with the simulations, the proposed compensation structure is a worthwhile guideline for the design of 3-D ICs.

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“…Several prior works [57][58][59][60][61][62][63][64] have analyzed coupling noise in 3D interconnects due to big-size TSVs. These studies focus on the placement stage, where the relative position of blocks and TSVs is fixed.…”

Section: Previous Workmentioning

confidence: 99%

“…Increasing TSV pitch is a commonly used technique for minimizing coupling noise in 3D circuits [58][59][60][61][62][63]. Previous works have either used force-directed algorithm to increase the KOZ around TSVs [58], or spreading the TSVs apart [59][60][61] to minimize TSV-to-TSV coupling. Both of these techniques will depend on the whitespace distribution around victim TSVs and therefore, offer limited solution quality.…”

Section: Nonuniform Tsv Pitchmentioning

confidence: 99%

Early Layout Design Exploration in TSV-based 3D Integrated Circuits

Ahmed¹

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Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage. The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10%-12% compared to wirelength-aware cost function. I would like to express my sincere gratitude to my advisor Prof. Malgorzata Chrzanowska-Jeske for the continuous support of my Ph.D. study and related research, for her patience, motivation, and immense knowledge. Her guidance helped me immensely in all the time of research and writing of this thesis. She was always available for my questions and gave generously for her time and vast knowledge. Besides my advisor, I would like to thank the rest of my thesis committee: Dr. W.

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Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling

Cited by 33 publications

References 25 publications

Coding Approach for Low-Power 3D Interconnects

Coding Approach for Low-Power 3D Interconnects

Electrical analysis of TSV step change in radius with compensation structure

Early Layout Design Exploration in TSV-based 3D Integrated Circuits

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