Silicon etching mechanism and anisotropy in CF4+O2 plasma

Abstract

From measurements of optical emission and silicon etch rate, we are able to separate contributions due to the chemical etching and the ion-bombardment enhanced etching in the CF4+O2 reactive ion etching process. The chemical etching part of undoped polysilicon etch rates is linearly proportional to the ground state fluorine population and the ion bombardment part is proportional to the dc self-bias voltage (V2.3bi). The chemical etching predominates during plasma etching, giving rise to the isotropic etch profile, while both the chemical etching and the ion-bombardment enhanced etching mechanisms coexist during reactive ion etching. A degree of the etch anisotropy in reactive ion etching is determined by competition between the chemical etching and the ion-bombardment enhanced etching, and can be expressed by an equation which only involves two physical quantities, etch rate and fluorine concentration, experimentally measurable in plasma etching and reactive ion etching. The silicon loading effect leads to a substantial decrease in a number density of the ground state fluorine and consequently makes an etch profile more directional by reducing a contribution due to the chemical etching. Also, we have identified important process parameters which influence etch profiles.

The ETCH Mechanism for Al2O3 in Fluorine and Chlorine Based RF Dry Etch Plasmas

“…This is significantly different from the exponent 2.5 suggested by Lee et al [2]. under physical sputtering conditions, the etch rates of the materials studied are all roughly proportional to Vdc squared, see table IV.…”

“…The exponent 1.26 for Si in CF +5%0 2 corresponds well with 1.3 ± .1 calculated for Si in CF 4 +20%0 2 [2]and with 1.4 ± .1 for Si in CF 4 ([13], assuming Vdc is equal to half of the rf peak voltage).…”

“…The measurements by Lee et al [2] and those done by Coburn [3] show that N is approximately proportional to Vdc. The measurements by Lee et al [2] and those done by Coburn [3] show that N is approximately proportional to Vdc.…”

“…THEORY Lee et al [2] suggested that the etch rate during reactive ion etching (ER) should be written as: THEORY Lee et al [2] suggested that the etch rate during reactive ion etching (ER) should be written as:…”

Plasma-etching processes for ULSI semiconductor circuits

“…For CMOS devices, use is made of polysilicon [56,57] gates. After patterning, the polysilicon is doped with an impurity, such as phosphorus, to make it electrically conductive.…”