Silicon-gate technology

Vadasz, L.; Grove, Andrew S.; Rowe, Tyler; Moore, Gordon E.

doi:10.1109/mspec.1969.5214116

Cited by 78 publications

(14 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A prime example is to use the gate of a MOSFET as a mask for defining the source and drain regions by means of ion implantation. 16,17 While most experiments employ electron spin states [5][6][7][8][9][10] to encode quantum information, hole spin qubits 11,18,19 represent an attractive alternative, particularly for large-scale quantum circuits. Hole spins in Si experience a strong spinorbit interaction (SOI), enabling rapid and allelectrical spin control.…”

mentioning

confidence: 99%

Silicon quantum dot devices with a self-aligned second gate layer

Geyer,

Camenzind,

Czornomaz

et al. 2020

Preprint

View full text Add to dashboard Cite

We implement silicon quantum dot devices with two layers of gate electrodes using a selfalignment technique, which allows for ultrasmall gate lengths and intrinsically perfect layer-to-layer alignment. In a double quantum dot system, we investigate hole transport and observe current rectification due to Pauli spin blockade. Magnetic field measurements indicate that hole spin relaxation is dominated by spin-orbit interaction, and enable us to determine the effective hole g-factor 1.6. From an avoided singlet-triplet crossing, occurring at high magnetic field, the spin-orbit coupling strength 0.27 meV is obtained, promising fast and all-electrical spin control.

show abstract

mentioning

confidence: 99%

Silicon quantum dot devices with a self-aligned second gate layer

Geyer,

Camenzind,

Czornomaz

et al. 2020

Preprint

View full text Add to dashboard Cite

show abstract

“…Initially, metal-oxide semiconductor field effect transistors (MOSFETs) had aluminum gates which were slow, large in area, unreliable, with high leakage currents. Then a self-aligned-gate process arrived in which the gates of the transistors were made with polycrystalline silicon [60], not a metal. The scaling of CMOS technology has accelerated in recent years and will arguably continue toward the 8 nm regime [4].…”

Section: Introductionmentioning

confidence: 99%

Nanoscale high-κ/metal-gate CMOS and FinFET based logic libraries

Yanambaka

Mohanty

Kougianos

et al. 2016

Nano-Cmos and Post-Cmos Electronics: Devices and Modelling

View full text Add to dashboard Cite

During the last four decades, VLSI technology growth has been driven by miniaturization that reduces cost per transistor, power consumption per transistor, with higher packing density and reduced cost of operation. However, the small transistor size leads to very high electric fields across the gate oxide which causes the difficult problem of gate oxide leakage. This problem is mitigated by high-κ/metal-gate technology, in which the gate material is copper (going back to metal from polysilicon) and the gate oxide material is a not silicon dioxide. At the same time, explosive growth of mobile portable electronics has been the driver for many scientific, engineering, and technological breakthroughs in the last few decades. Mobile electronics in particular, such as smart mobile phones, spend most of their operational time in waiting for a call or similar event. However, during these wait states leakage power dissipation has been a major issue since it drains the battery continuously. The industry has explored various solutions to reduce the OFF state leakage and multiple gate devices emerged as a solution to this problem. Double gate FinFET technology is considered as a solution to reduce OFF state leakage while having faster ON and OFF transitions and low-power dissipation. This chapter discusses these devices and presents logic libraries which can be used in the digital synthesis of large integrated circuits using such devices through electronic design automation (EDA) tools.

show abstract

“…For decades, semiconductor manufacturers have been shrinking transistor size in ICs to achieve the yearly increases in speed and performance described by Moore's Law, which exists only because the RC delay was negligible in comparison with signal propagation delay [1]. For submicron technology, however, the RC delay becomes a dominant factor [2].…”

Section: Introductionmentioning

confidence: 99%

A novel methodology for architecture-level exploration of 3D SoCs

Diamantopoulos

Siozios

Bekiaris

et al. 2011

2011 6th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

View full text Add to dashboard Cite

Three-dimensional (3D) integration is an emerging technology that is expected to lead to tremendous benefits in terms of power, delay and silicon area. Moreover, 3D technology continues interconnect advances beyond the CMOS scaling predicted by Moore's Law, which enable new capabilities not available in 2D ICs. This paper proposes a physical design framework that enables rapid evaluation of 3D SOCs under different optimization goals. For demonstration purposes we apply the proposed framework for the 3D physical design of an embedded processor. Experimental results shown that 3D integration can alleviate the constraints posed by increased wirelength, such as power consumption, by about 20% compared to the 2D implementation.

show abstract

Silicon-gate technology

Cited by 78 publications

References 5 publications

Silicon quantum dot devices with a self-aligned second gate layer

Silicon quantum dot devices with a self-aligned second gate layer

Nanoscale high-κ/metal-gate CMOS and FinFET based logic libraries

A novel methodology for architecture-level exploration of 3D SoCs

Contact Info

Product

Resources

About