Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems

Iyer, Subramanian S.; Jangam, SivaChandra; Vaisband, Boris

doi:10.1147/jrd.2019.2940427

Cited by 33 publications

(3 citation statements)

References 34 publications

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“…This new platform is adapted from the silicon interconnect fabric (Si-IF) developed at UCLA [19][20][21][22]. The Si-IF is an advanced packaging technology that owns characteristics, including system-on-silicon-wafer, fine pitch ( 10 μm), short inter-dielet spacing ( 100 μm), metal-to-metal bonding, no solder and underfill, high bandwidth, low energy consumption per bit and low latency.…”

Section: Assembly Methodsmentioning

confidence: 99%

Nb-based superconducting silicon interconnect fabric for cryogenic electronics

Yang¹,

Hu²,

Zhang³

et al. 2021

Quantum Sci. Technol.

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Quantum computing for real world applications requires large arrays of qubits. This requires advanced integration technologies. In this work, we propose a simple integration method with fine interconnect pitch (10 μm) and close spacing that can overcome the large input and output (I/O) and high wiring level requirements of very large scale of quantum circuits. A system-on-wafer (SoW) packaging concept called superconducting silicon interconnect fabric (superconducting-IF), based on silicon interconnect fabric (Si-IF), is proposed, with the help of a Au interlayer technology onto the superconducting-IF. The fine-pitch and die-to-wafer-scale Au interlayer is the first demonstration of direct metal–metal thermocompression bonding (TCB) that is optimized for superconducting applications without the use of solders. The developed Au interlayer integration technology is demonstrated to be Josephson-junction-compatible (<150 °C), mechanically robust (>30 MPa), and electrically reliable down to 2 K. The mechanical strength of the Au interlayer integration method is optimized through shear tests with a shear force around 150 N on 2 × 2 mm2 dies. The transition temperature (Tc) of Nb, which is at 9 K, is experimentally verified to be unchanged after each fabrication process. Electrical and temperature cycling measurements on over 20 bonded dies of large-pitch Kelvin structures as well as fine-pitch daisy chain structures reveal reliable connections in the low-temperature regime. This work pushes quantum computing a step closer to realize its potential through 3D integration of a very large scale of quantum circuits with a high density of I/O (>10 000 per mm2) as well as high wiring capability and without introducing lossy amorphous dielectrics.

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Section: Assembly Methodsmentioning

confidence: 99%

Nb-based superconducting silicon interconnect fabric for cryogenic electronics

Yang¹,

Hu²,

Zhang³

et al. 2021

Quantum Sci. Technol.

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“…Wit h t he capabi l it y for h ig hthroughput chip-to-chip data transmission, chiplet technology provides the potential for incorporating hardware accelerators for machine learning, AI, or neuromorphic computing. 5,6 Chiplets enable the hardware accelerators to be designed and manufactured using ideal and custom technologies while still maintaining low-latency communication with the central processor. Research in this area is active with universities and industry groups, who report chiplet-based accelerators for machine learning and signal processing, taking advantage of interchip data rates exceeding 1 Tb/s.…”

Section: Microelectronicsmentioning

confidence: 99%

Exploring Heterogeneous Integration: Its Essence and Future Path

Nordquist,

Chou

2024

Computer

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Heterogeneous integration (HI) is the integration of chiplets using packaging technologies. Whereas a traditional system on chip (SoC) uses semiconductor technologies to integrate functionalities on a single silicon wafer, HI looks to disaggregate the functionalities of a SoC into smaller chiplets, or use proven intellectual properties (IPs) and older technologies and repackage them into a new product built for specific applications. This approach of producing a system in package (SiP) has proven attractive, especially as the progress of Moore's law has waned. Indeed, for the bulk of our lifetime, Moore's law has allowed transistor densities to double every two years. This fueled the integration of increasingly complex functionalities into a single silicon chip and the aggregation of multiple functionalities, including the CPU, graphics processing, custom accelerators, memor y, and input-output functionalities. However, as the transistor integration approaches billions per chip, the economic and technological drivers are steering manufacturers away from monolithic integration. Here, as monolithic chip sizes swell to the size of a reticle, the yield of a monolithic SoC falls appreciably because of defects in the semiconductor manufacturing process. Consequently,

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“…[1,2,5,6] Recently, there has been interest in additive "direct write" approaches as an alternative method of nanofabrication with two significant opportunities for their utilization.The first opportunity is in HI: creating dense interconnects between many chiplets with diverse functions and geometries that are integrated on large panels or packages, often organic substrates. [3,28,29] Chiplet integration addresses the needs for energy-efficient computing and the need for fast access to lots of memory. [3,29] The area of a single chip is ultimately limited by the reticle size during lithography, hence the integration of multiple chiplets is necessary.…”

mentioning

confidence: 99%

Nanofabrication and Demonstration of a Direct‐Write Microevaporator

Doi,

Nittala,

et al. 2023

Small Science

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Direct‐write vapor deposition is a new technique that would enable one‐step 3D maskless nanofabrication on a variety of substrates. A novel silicon chip‐based microevaporator is developed that allows evaporant to exit through 2000–300 nm nozzles while held at distances comparable to the nozzle diameter from the substrate by a three‐axis nanopositioning stage in vacuum. This results in a localized deposition on the substrate, which may be scanned relative to the substrate to produce direct‐write patterns. The performance of the microevaporator is tested by creating localized depositions of various materials and the line‐writing potential is demonstrated. The relationship between linewidth and source‐to‐substrate distance is investigated by the application of Knudsen's cosine law and Monte‐Carlo simulations, and then utilized to approximate the source‐to‐substrate distance from performed depositions.

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Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems

Cited by 33 publications

References 34 publications

Nb-based superconducting silicon interconnect fabric for cryogenic electronics

Nb-based superconducting silicon interconnect fabric for cryogenic electronics

Exploring Heterogeneous Integration: Its Essence and Future Path

Nanofabrication and Demonstration of a Direct‐Write Microevaporator

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