Silicon interlayer-based oxide-free surface passivation of InP and its application to MISFETs

Abstract

Novel silicon interlayer-based oxide-free surface passivation is described and applied to fabrication of metal-insulator-semiconductor field effect transistors (MISFETs). Surface quantum states formed in the band lineup of SiN,/Si/InP were pushed away by the quantum confinement effect by reducing the Si interlayer thickness down to about 5 A. Formation of the desired interface structure was confirmed by X-ray photoelectron spectroscopy (XPS) measurement. Ultrahigh vacuum (UHV) contactless capacitance-voltage (C-V) measurement was used for optimization of the process. InP surface after in situ passivation using the Si interlayer realized a full swing of Fermi level almost over the entire bandgap. The fabricated MISFETs with the Si interlayer-based passivation exhibited excellent gate control capability and stable operation with a low gate leakage current. The drift of the drain current was found to be as small as 1.9% after 104 s operation.