Silicon nanoarray circuits design, modeling, simulation and fabrication

Abstract

We developed a methodology for the design and fabrication of silicon nanowire-based circuits. Starting from a functional description of the circuit and using technological data, we generated the physical design of the described function by placing nanowires, FETs and connections. We modeled each circuit sub-block considering resistances, capacitances and FET currents, taking into account gate quantum capacitance. We extracted a post-layout netlist of the whole circuit, suitable for a detailed spice simulation. As an example, we executed an ELDO simulation for a 2-bit adder demonstrating unprecedented capabilities with respect to the nanoarray related literature. We show our fabrication experiments based on Metal-assisted Etching and we are now ready for devices characterization and models validation. I. INT RODUCTION Silicon Nanoarray structures are increasingly ansmg the scientific interest for their expected regularity, compact ness and performance in terms of computation capabilities [1][2]. These are based on silicon nanowires that are or ganized in matrices [3], where active nanodevices (diodes and FETs) are created at their crosspoints. The authors in [4][5] propose the NASIC as an improvement over general purpose programmable fabrics (PLAs) since, according to their proponents, they lead to denser designs with better fabric utilization and circuit cascading. These structures are basically two dimensional tiled arrays, and authors in [6] show how massively parallel architectures can be made out of these fabrics. The literature shows studies both at the architec tural [1][7][8] level, and at the device/technological level [2] [9] [lO]. These important studies attempt, on one side, to better understand the workings of prospective devices by means of numerical simulations of innovative structures or by the development of new models for few-nanometer scale devices. On the other side, they aim to devise proper circuit architectures to unleash the characteristics of future active devices in terms of speed of operation, power consumption, reliability, etc. The work in [1] shows a preliminary attempt to cross the bridge between device technology and architecture design, by extracting device characterization with a numerical simula tion tool, and creating a table model out of simulated device, to be used into circuit-level simulations. This approach is promising, because it goes into the direction of connecting proper device characterization with circuit-level information extraction. However, in order to explore the real potentialities of nanoarrays, the evaluation of circuits of realistic complexity is necessary, not only with simplified estimations based on model devices and ideal circuits, but also by considering the physics of devices and wires post circuit realization. For example, all the parasitics involving the actual design should be taken into account, and the simulation should capture also the variability in device characteristics due to the fabrication process. The inner complexity of this approach actua...

Fault tolerant nanoarray circuits: Automatic design and verification

“…They represent the cases in which an error is propagated towards the output for a given logic state in a given plane (where the symbol • used in Eq. [3] and [4] is the Hadamard product), and where R ok plane = 1 − R on plane − R off plane represents the probability of having TRs with no faults.…”

“…Nanoarray circuits represent the beyond-CMOS technology nearer to scaled CMOS [1] [2] [3]. Proposed circuits topologies have in common the elementary device, i.e.…”

“…Both characteristics are predictive of high compactness, good trade-off between power and frequency, and remarkable predisposition for massive parallel computation [4] [5]. Nevertheless defects will be for long time one of the main concerns from the technology side [3] [6]. Though experimental demonstrations have been already presented [7] [2], processes are still not mature.…”

Methodology modeling of MaE-fabricated Porous Silicon Nanowires

“…Silicon Nanowires (Si-NWs) are largely being studied in the emerging scenario of (nano)electronics for their versatile properties, their obvious integrability with standard Silicon based technologies, and for the fabrication techniques in several cases exploiting techniques based on self-assembly not requiring lithographic processes. A major distinction should be done between pure-cristalline Si-NWs, mainly used for computation applications [1]- [3] and NWs presenting an irregular, non cristalline, i.e. porous, structure.…”