Silicon nanotube SRAM and its SEU reliability

Jayakumar, Ganesh; Srinivasan, R.

doi:10.1016/j.spmi.2017.03.057

Cited by 4 publications

(2 citation statements)

References 17 publications

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“…Butterfly curves are utilised to quantify the SNM in all the three modes. Butterfly curves are obtained by superimposing the voltage transfer characteristic of both the inverters [18]. The butterfly curve obtained for different mode of DS-JLSiNT FET, D-JLSiNT FET, and S-JLSiNT FET based 6T-SRAM cell are compared in Fig.…”

Section: T Sram Design and Analysismentioning

confidence: 99%

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Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

Tayal

Nandi

2018

Micro & Nano Letters

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This work investigates the delay performance of junctionless silicon nanotube (JLSiNT) field-effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay performance of symmetric drain/source DS-JLSiNT FET (inner gate covers drain, channel, and source regions) based 6T SRAM gets improved when the inner gate of nanotube covers only either drain and channel regions (D-JLSiNT FET) or source and channel regions (S-JLSiNT FET) because of improved I on /C gg. The improvement in read (write) access time is ∼22% (17%) and ∼9% (20%) when DS-JLSiNT FET is replaced by D-JLSiNT FET and S-JLSiNT FET, respectively, in DS-JLSiNT FET based 6T SRAM. Furthermore, due to partial covering of inner gate, the gate electrostatic integrity is reduced which decreases the ratio of on-current to off-current (I on /I off) resulting in degraded static noise margin (SNM). However, the deterioration in write SNM, hold SNM, and read SNM are almost minimal (∼0.3, 0.9, and 2%, respectively) for S-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. However, the deterioration in SNMs is aggravated for D-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. Thus, S-JLSiNT FET is the best configuration for designing of JLSiNT FET based 6T SRAM cell.

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Section: T Sram Design and Analysismentioning

confidence: 99%

“…Recently, SiNT FET based 6T SRAM has been investigated by Jayakumar and Srinivasan [18]. However, a comprehensive study on delay performance of JLSiNT FET 6T SRAM is still critically required.…”

Section: Introductionmentioning

confidence: 99%

Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

Tayal

Nandi

2018

Micro & Nano Letters

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Study of 6T SRAM cell using High- K gate dielectric based junctionless silicon nanotube FET

Tayal

Nandi

2017

Superlattices and Microstructures

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Soft error study on junctionless silicon nanotube FET based 6T SRAM cell

Durga

Srinivasan

2020

J. Phys.: Conf. Ser.

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In this work, the response of Junctionless Silicon Nanotube FET (JL SiNT FET) to the heavy ion irradiation and the soft error performance of JL SiNT FET based SRAM circuit are investigated using 3D numerical simulations. The impact of single event transient (SET) is studied at different locations of junctionless SiNT with different incident angles to identify the sensitive location of the device. After SET analysis, JL SiNT FET based 6T SRAM cell is studied for single event upset (SEU). Heavy ion study of JL SiNT FET is compared with junction based SiNT FET. The simulation result shows that the threshold linear energy transfer (LETth) of JL SiNT FET based SRAM is approximately three times lesser than the junction based SiNT FET SRAM.

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Silicon nanotube SRAM and its SEU reliability

Cited by 4 publications

References 17 publications

Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

Study of 6T SRAM cell using High- K gate dielectric based junctionless silicon nanotube FET

Soft error study on junctionless silicon nanotube FET based 6T SRAM cell

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