Silicon nanowire fabrication

Abstract

Purpose – The purpose of this study is to present reports on fabrication of silicon (Si) nanowires (NWs). The study consists of microwire formation on silicon-on-insulator (SOI) that was fabricated using a top-down approach which involved conventional photolithography coupled with shallow anisotropic etching. Design/methodology/approach – A 5-inch p-type silicon-on-insulator (SOI) coated with 250nm layer and Photoresist (PR) with thickness of 400nm is coated in order to make pattern transfer via binary mask, after the exposure and development, a resist pattern between 3 μm-5 μm were obtained, Oxygen plasma spreen was used to reduce the size of the PR to 800 μm, after this, the wafer with 800 μm was loaded into SAMCO inductively coupled plasma (ICP)-RIE and got silicoon microwire was obtained. Next, the sample was put into an oxidation furnace for 15, 30, 45 and 60 minutes and the sample was removed and dipped into a buffered oxide etch solution for five minutes to remove all the SiO2 ashes. Findings – The morphological characterization was conducted using scanning electron microscopy and atomic force microscopy. At terminal two, gold electrodes which were designated as source and drain were fabricated on top of individual NWs using conventional lithography electrical and chemical response. Once the trimming process has been completed, the device's current–voltage (I-V) characteristic was measured by using a Keithley 4200 semiconductor parameter analyser. Devices with different width of wires approximately 20, 40, 60 and 80 nm were characterized. The wire current variation as a function of the pH variation in voltage was investigated: pH monitoring for variations of pH values between 5 and 9. Originality/value – This paper provides useful information on novel and yet simple cost-effective fabrication of SiNW; as such, it should be of interest to a broad readership, especially those interested in micro/nanofabrication.

Piezoresistive characterization of bottom-up, n-type silicon microwires undergoing bend deformation

“…7,8 Studies at the microscale have been limited and mainly focused on microwires developed through top-down fabrication processes involving etching of lithographically patterned silicon wafers. 9,10 However, there are fewer reports of studies performed on microwires grown via bottom-up chemical vapour deposition (CVD), in which silicon microwires are seeded with a metallic catalyst and grown using a vapour-liquid-solid (VLS) process. 11 Wires grown bottom-up exhibit characteristics distinct from top-down microwires, including faceted surfaces and the incorporation of metallic impurities.…”