Silicon-on-Insulator Technology: Materials to VLSI

Abstract

Library of Congress Cataloging-in-Publication Data Colinge, lean-Pierre.Silicon-on-insulator technology : materials to VLSI / by leaD -Pierre Colinge.p. cm. -(The Kluwer international series in engineering and computer science ; SECS 132. VLSI, computer architecture, and digital signal processing)Includes bibliographieal references and index.

Silicon on Insulator Technology Review

“…Furthermore, Intel has recently unveiled their vision of the CMOS device they will pursue in the future, to achieve continuous scaling of CMOS with high performance and acceptable power (and voltage) requirements. This is the Intel "Terahertz Transistor", which employs the use of a fully depleted (FD) CMOS transistor on thin SOI wafers [7], among other design changes (such as high-K gate dielectric and raised source-drain regions).…”

“…One of the more compelling reasons why support for migration from bulk to SOI CMOS is growing is due to the problems created by the exponential growth of the power dissipated by high performance, high density CMOS ICs in bulk (or epitaxial) silicon as scaling has been pursued [7]. For example, as Intel microprocessors have evolved by scaling through the 286, 386, and 486 generations into and through the Pentium generations, power dissipation has dramatically (exponentially) increased.…”

“…Consequently, it is expected that FD SOI CMOS transistors will be generally adopted in the near future [1,68,48]. Converting an existing PD SOI CMOS device and circuit design into FD CMOS is expected to be straightforward [7,9], at least in comparison with to the challenges in the conversion from bulk CMOS to SOI CMOS.…”

Cristallisation du silicium amorphe par laser à excimères

“…L'irradiation, a été effectuée à 580 mJ/cm 2 , avec un recouvrement de faisceau de 90%, tandis que le substrat était maintenu à 350°C [17]. Les caractéristiques de ces TFTs sont bien meilleures que celles présentées plus haut (mobilités n et p de 350 et 150 cmVVs, tensions de seuil n et p de 1,2 et -2,4 V) et elles deviennent comparables à celles de MOSFETs fabriqués dans du silicium monocristallin sur isolant [7], attestant de la grande qualité des films obtenus par cristallisation laser. On peut apprécier cette qualité cristalline sur la photo de microscopie à transmission présentée figure 8.…”

Efeito da tensão mecânica no ruído de baixa frequência de transistores SOI planares e tridimensionais.

“…Os resultados mostram que os transistores tensionados são capazes de promover um melhor desempenho na transcondutância, na ordem de um aumento no mínimo de 40% , indicando para comprimentos longos de canal (910 nm) uma aumento de 56% para tensão mecânica biaxial e o oposto para a uniaxial (45%) (160 nm): entretanto, na condutância de saída, a tensão mecânica de forma geral promove uma maior degradação, aumento de 3% para um transistor uniaxial e aumento de 105% para o transistor biaxial. No ganho intrínseco de A tecnologia SOI consiste em isolar a região ativa do transistor formada pela camada de silício do substrato, eliminando assim alguns efeitos parasitários (4,2) decorrentes da interação do substrato com a camada de silício. Podemos citar como benefícios obtidos pela isolação da região ativa a redução dos efeitos de canal curto (5), os aumentos da transcondutância e da mobilidade (6), a redução das capacitâncias parasitárias de fonte e de dreno (7) e a melhora na inclinação de sublimiar.…”