Silicon Oxidation Studies: Silicon Orientation Effects on Thermal Oxidation

Irene, E. A.; Massoud, Hisham Z.; Tierney, E.

doi:10.1149/1.2108829

Cited by 93 publications

(67 citation statements)

References 15 publications

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“…intrinsic stress (10,24), the diffusion rate and thus C, would be reduced the most on this orientation. The diffusion process, and The areas of all five orientations are given in Table 6.…”

Section: (511) > (311) > (110) > (111) > (100)mentioning

confidence: 97%

“…The order of the rates as a function of orientation is complex and depends on oxide thickness (7-9), oxidation temperature (3,7-9), and ambient pressure (1,6-8). In the initial stages of oxidation at 1 atm the rates are in the order (110) > (111) > (100), but within the first 25 nm of oxide formed, the order is reversed on the (110) and (111) orientations at temperatures in the range 750-1000--C (7,(9)(10)(11). The thickness where the rate crossover occurs varies slightly with oxidation temperature, increasing with increasing temperature (7).…”

Section: Introductionmentioning

confidence: 99%

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The Effect of Surface Orientation on Silicon Oxidation Kinetics

Lewis

Irene

1987

J. Electrochem. Soc.

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The rate of thermal oxidation of silicon is orientation dependent indicating that the surface orientation is an important parameter in the kinetic mechanism. However, it has not been clearly established which properties of the silicon surface control the oxidation rate. This study uses five silicon surface orientations to investigate the effect of the density of silicon atoms on planes parallel to the surface and the effect of intrinisic oxide stress on the oxidation rates. At temperatures of 700 ~ 1000 ~ and 1100~ the initial order of the rates is (110) > ( 111) > ( 311) > ( 511) > ( 100). The crossover in rate to (111) > ( 110) was observed at 700 ~ and 1000~ but not at 1100~ A qualitative correlation is obtained between the order of the initial rates and the density of atoms on the five planes. Stress effects do not appear to be dominant in the thickness regime before the rates on the (110) and (111) orientations crossover, but the ll00~ results suggest that the crossover may be related to the development of intrinsic oxide stress at lower temperatures. A revised explanation of the crossover on the (110) and ( 111) orientations based on a stress-related decrease in the transport of oxidant to the interface is proposed.

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“…intrinsic stress (10,24), the diffusion rate and thus C, would be reduced the most on this orientation. The diffusion process, and The areas of all five orientations are given in Table 6.…”

Section: (511) > (311) > (110) > (111) > (100)mentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

The Effect of Surface Orientation on Silicon Oxidation Kinetics

Lewis

Irene

1987

J. Electrochem. Soc.

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“…density. 9 However, from the HRTEM images, it is clear that the oxide surface layers are conformal on both the (100) and (111) surfaces and very nearly the same thickness. All in all, these results suggest that the presence of boron is very strongly influencing the rate of oxidation.…”

Section: 4nm (B)mentioning

confidence: 99%

Effects of Annealing on Chemical-Vapor Deposited PureB Layers

Rine

Vlooswijk

Mohammadi

et al. 2013

ECS J. Solid State Sci. Technol.

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Chemical-vapor-deposited pure boron (PureB) layers can be used as a source of p-type boron dopants for thermal diffusion into silicon during a drive-in anneal. In this work, the effect of thermally annealing PureB layers is investigated in terms of surface morphology and electrical properties. The presence of a few nanometer-thick PureB layer on the Si surface was found to increase the silicon oxide growth rate by several factors during annealing in an oxygen-containing atmosphere. The oxide thickness was dependent on the initial PureB layer thickness and oxygen concentration during anneal. In an oxygen-limited atmosphere, the final thickness is insensitive to the anneal temperature as the reaction is diffusion-limited and, after oxide removal, a hydrophilic boron rich layer remains on the Si surface. With a high oxygen concentration, the boron is depleted by an oxidation of the boron-doped silicon resulting in a lower surface concentration and higher sheet resistance. A reaction mechanism involving the oxidation of Si-B compounds to form B 2 O 3 is proposed to explain the experimental observations. With solar cell and other photodiode applications in mind, the sheet resistance and carrier lifetime measurements were performed and show that a one-step oxidation process can simultaneously drive-in the dopants and form an oxide passivation layer. The chemical vapor deposition (CVD) of pure boron (PureB) layers has in recent years been successfully applied for fabricating extremely shallow, less than 10-nm deep, silicon p + n junction diodes. 1This has provided impressive performance of bulk-Si photodiodes for detecting low penetration-depth beams. 2,3 Ideal low-leakage diode characteristics are achieved for deposition temperatures from 400 to 700• C. 4 In addition, the 700 • C PureB deposition can be deposited with well-controlled uniformity and reproducibility down to a thickness of 2 nm in a conformal manner with high selectivity to silicon rather than silicon oxide, 5 making this technology attractive for advanced device architectures.From studies of the quantum efficiency of VUV photodiodes 3 fabricated with PureB anode regions subjected to various drive-in procedures it has been found that high efficiencies are maintained despite the increase in junction depth from a few nanometers to the hundred-nanometer range. This is accorded to the defect-free nature of the doping process and the lack of roll-off at the surface of the resulting doping profiles. These features are also attractive for the manufacture of p + emitter layers for solar cells and for the passivation of depleted interfaces in other types of photodiode structures. A batch furnace system for the CVD of PureB is currently being developed for high-throughput industrial applications. 6 For application in standard n-type crystalline silicon solar cells, substantial drive-in is required to achieve the dopant profiles and sheet resistance necessary for a low series resistance through the p-type surface layers and associated contacts. More critically, a w...

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“…After formation of the fin structure, which had a surface tilted from the (110)-oriented side surfaces, the fin structure was oxidized in dry oxygen ambient for 1 h at 1000 C. We considered that the oxidation rate dependence on the surface orientation 22 becomes dominant, which leads to the formation of the facet at the SiNW channel surface. We propose a schematic model of the side surface that is composed of (110)-and (100)-faceted surfaces of the asymmetric SiNW nFET to explain the dependence of l SR on the measurement conditions.…”

mentioning

confidence: 99%

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Sato

Kakushima

Ohmori

et al. 2011

Applied Physics Letters

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This letter reports the electrical characteristics of nonuniform silicon nanowire nFETs with asymmetric source and drain widths. For electrostatic properties, reduced drain-induced barrier lowering (DIBL) is achieved in a device in which the source is wider than the drain. For carrier transport properties, higher values of surface-roughness-limited mobility (l SR ) are obtained in the sample with the wider drain size. Our electrostatic model shows that the concentration of lines of electric force is relaxed near the wider source edge, which results in smaller DIBL. The asymmetric l SR is attributed to the channel surface morphology with (110)-and (100)-faceted surfaces.

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Silicon Oxidation Studies: Silicon Orientation Effects on Thermal Oxidation

Cited by 93 publications

References 15 publications

The Effect of Surface Orientation on Silicon Oxidation Kinetics

The Effect of Surface Orientation on Silicon Oxidation Kinetics

Effects of Annealing on Chemical-Vapor Deposited PureB Layers

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

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