Silicon Photonic Integration Platform—Have We Found the Sweet Spot?

Abstract

The current trend in silicon photonics towards higher levels of integration as well as the model of using CMOS foundries for fabrication are leading to a need for standardization of substrate parameters and fabrication processes. In particular, for several established research and development foundries that grant general access, silicon-oninsulator wafers with a silicon thickness of 220 nm have become the standard substrate for which devices and circuits have to be designed. In this study we investigate the role of silicon device layer thickness in design optimization of various components that need to be integrated in a typical optical transceiver, including both passive ones for routing, wavelength selection, and light coupling as well as active ones such as monolithic modulators and on-chip lasers produced by hybrid integration. We find that in all devices considered there is an advantage in using a silicon thickness larger than 220 nm, either for improved performance or for simplified fabrication processes and relaxed tolerances.

High-power sub-kHz linewidth lasers fully integrated on silicon

“…The last point is particularly important, because the ULL silicon platform uses the same silicon thickness (500 nm) as the heterogeneous silicon/III-V laser. The 500 nm thick silicon can achieve index matching between the silicon waveguide and the III-V epitaxial stack to provide a suitable Si/III-V hybrid mode in the gain section [34][35][36]. The use of a thick (500 nm) silicon layer has also been demonstrated to support high linearity heterogeneous silicon/III-V modulators [37] with high operating power [38], and high bandwidth photodetectors [9].…”

Manipulating the flow of light using Dirac-cone zero-index metamaterials

“…While achievement of a ZIM has a significant depend ence on pillar height, compatibility with existing integrated platforms limits heights to those available in commercial silicon-on-insulator (SOI) wafers with lower device thicknesses. This is par ticularly challenging for the TM modes associated with dielectric pillars as there is a stricter dependence on minimum height necessary to support the modes [111,112].…”

Multimode Waveguides on an SOI Platform for Arbitrary Power Splitting Ratio Couplers

“…The simulation shows that the changes in normalized output powers are very small (nearly 0% in the range of À50 nm to +50 nm). It is feasible for the current CMOS circuitry [31].…”