2013
DOI: 10.1016/j.neucom.2012.01.042
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Silicon spiking neurons for hardware implementation of extreme learning machines

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Cited by 76 publications
(37 citation statements)
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“…In [84], the components of VLSI implementation of a spiking neural network is presented while [85] demonstrates a highly configurable neuromorphic chip with integrated learning for a network of spiking neurons which can be used in pattern classification, recognition, and associative memory tasks. A spatial architecture named 'Eyeriss' for energy-efficient dataflow for Convolutional Neural Networks is implemented in [86].…”
Section: Advanced Technologies For ML Hardware Architecturementioning
confidence: 99%
“…In [84], the components of VLSI implementation of a spiking neural network is presented while [85] demonstrates a highly configurable neuromorphic chip with integrated learning for a network of spiking neurons which can be used in pattern classification, recognition, and associative memory tasks. A spatial architecture named 'Eyeriss' for energy-efficient dataflow for Convolutional Neural Networks is implemented in [86].…”
Section: Advanced Technologies For ML Hardware Architecturementioning
confidence: 99%
“…Where g(a,b,x) is an activation function satisfying ELM universal approximation capability theorems [11]. In fact, any nonlinear piecewise continuous functions (e.g.…”
Section: Extreme Learning Machinementioning
confidence: 99%
“…Numerous implementations of multi-layered extreme learning machines have been developed [27][28][29], and it was found that the multi-layer implementation of extreme learning machine performed better than the conventional ELM in term of the recognition and classification performance. Recent works that were intended to develop neuromorphic implementations of Extreme Learning Machines [30][31][32] motivated this current work. Further details of neuromorphic implementations are described elsewhere [33].…”
Section: Introductionmentioning
confidence: 99%