SimCommSys: taking the errors out of error‐correcting code simulations

Abstract

In this paper we present SimCommSys, a Simulator of Communication Systems that we are releasing under an open source license. The core of the project is a set of C++ libraries defining communication system components and a distributed Monte Carlo simulator. Of principal interest is the error-control coding component, where various kinds of binary and nonbinary codes are implemented, including turbo, LDPC, repeataccumulate, and Reed-Solomon. The project also contains a number of ready-to-build binaries implementing various stages of the communication system (such as the encoder and decoder), a complete simulator, and a system benchmark. Finally, Sim-CommSys also provides a number of shell and python scripts to encapsulate routine use cases. As long as the required components are already available in SimCommSys, the user may simulate complete communication systems of their own design without any additional programming. The strict separation of development (needed only to implement new components) and use (to simulate specific constructions) encourages reproducibility of experimental work and reduces the likelihood of error. Following an overview of the framework, we provide some examples of how to use the framework, including the implementation of a simple codec, the specification of communication systems and their simulation.

Recent Results on the Implementation of a Burst Error and Burst Erasure Channel Emulator Using an FPGA Architecture

“…Moreover, the Reed Solomon code described above, once added in the processing chain, has been verified to have an error correction capability matching exactly the Reiger's bound [35]. 4 The choice of k = 188 was determined by the requirement, considered important at the beginning of the 1990's, to facilitate the transfer of compressed audio and video information on radio bridge and satellite communications systems, based on the asynchronous transfer mode (ATM) standard. This system, designed for telephone switching and transmission, requires data to be organized in cells of 53 bytes, of which 48 bytes of data and 5 bytes of header.…”

“…In this module, the length of the error burst is programmable by means of a 4-bit bus: thus, 16 different values may be selected. The binary configurations of the switches SW [2][3][4][5], through which it is possible to choose the duration of the error burst or erasure burst are reported in Table I of [22].…”

“…1) CPU implementations using: a) the software tool Matlab [1]: see, e.g., [2], in which four Matlab programs to simulate the Markov fading channel were developed, and [3], where a burst error correction scheme was implemented; b) the C/C++ libraries and interface: see, e.g., [4]; 2) GPU implementations: see, e.g., [5], where the parallel error-resilient entropy coding (P-EREC) is shown to increase the resilience of the variable-length coding (VLC) bit-stream to random and burst errors, or [6], Manuscript where a real-time RS decoding is obtained using a GPU direct transfer; 3) hardware measurement platforms: see, e.g., [7], where a single-hop network running the point-to-point protocol (PPP) connects a mobile host to a fixed host terminating a circuit-switched global system for mobile communications (GSM) connection, or [8], where the traces of traffic are taken from a 2.5 Gb/s interface of a broadband access router of Deutsche Telekom's internet protocol (IP) platform, connecting residential asymmetric digital subscriber line (ADSL) access lines to the backbone; 4) FPGA implementations: see, e.g., [9], where forward error correction (FEC) based on Reed-Solomon (RS) codecoding was implemented on an FPGA, or [10], where an FPGA implementation of a channel co-decoder, interleaver and deinterleaver is presented, considering a Multiple Input and Multiple Output (MIMO) technology. The simulation of the burst erasure channel -which is also important given the different real scenarios in which this channel model may be applied (see next section) -has been widely considered as well in the recent literature through:…”

“…1) CPU implementations using: a) the software tool Matlab: see, e.g., [11], where hybrid serial concatenated network codes are proposed to contrast burst erasures, and [12], where erasure-correcting codes are designed for channels with burst and random erasures; b) the C/C++ libraries and interface: see, e.g., [4] and [13]; 2) GPU implementations: see, e.g., [14], where low-density generator matrix (LDGM) coding is proposed for counteracting long loss bursts, or [15], where the speed and accuracy of the quasi-cyclic low-density parity check (QC-LDPC) simulations are shown to be greatly increased by utilising the parallel architecture of GPUs; 3) hardware measurement platforms: see, e.g., [7], where artificial traces are generated with the same statistical characteristics as actual collected network traces, or [16], where real video and aggregated Internet traces are used to study the delay per packet in a burst erasure; 4) FPGA implementations: see, e.g., [17], where a design and FPGA implementation of a reconfigurable FEC decoder based on a RS code for WiMax networks is presented, or [18], where the RS decoder performance is reviewed as far as its FPGA implementations are concerned. As put in evidence by the above presented literature overview, the simulation of a transmission channel behaviour may be implemented using the performance abilities of current generation multiprocessing hardware, namely, a multicore CPU, a general purpose GPU, or an FPGA.…”

A Survey on Error–Correcting Codes for Digital Video Broadcasting

“…The authors of [19] present a comprehensive survey of ECC for channels corrupted by synchronization errors; they discuss potential applications used in sound systems without mentioning its importance in the DVB system. Different types of ECC are simulated under SimCommSys [20] in communication systems. Most coding schemes focus on the correction of substitution errors; the problem of correcting synchronization errors has seen a recent increase in interest [19].…”