SIMD array on FPGA for B/W image processing

Nieto, Alejandro; Brea, V.M.; Vilariño, D.L.

doi:10.1109/cnna.2008.4588678

Cited by 6 publications

(8 citation statements)

References 5 publications

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“…The proposed architecture possesses some similarities with the design described in [16] but there are some differences which make the proposed design more flexible. Firstly, there is a more versatile ALU providing additional operations such as an adder and XOR function in addition to all the functions offered in [16].…”

Section: By the Dashed Lines)mentioning

confidence: 91%

“…Firstly, there is a more versatile ALU providing additional operations such as an adder and XOR function in addition to all the functions offered in [16]. As well as this, the proposed architecture has 256 bits of RAM as opposed to eight 1-bit registers for local storage allowing for the storage of larger images or even multiple images.…”

Section: By the Dashed Lines)mentioning

confidence: 99%

“…The design in [16] presents a 48 × 48 processor array that performs binary operations showing FPGAs to be capable of implementing moderate sized fine grained processor arrays which could even be scaled up to larger FPGAs. Even though FPGAs cannot offer performance as high as ASICs and despite their lower frequency of operation, they can still offer significant performance due to their parallel nature, with their overall performance being limited by FPGA size [17].…”

Section: Introductionmentioning

confidence: 99%

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A compact FPGA implementation of a bit-serial SIMD cellular processor array

Walsh

Dudek

2012

2012 13th International Workshop on Cellular Nanoscale Networks and Their Applications

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An FPGA implementation of a fine grain generalpurpose SIMD processor array is presented. The processor architecture has a compact processing element which is encapsulated into two configurable logic blocks (CLBs) and is then replicated to form an array. A 32 × 32 processing element array is implemented on a low-cost Xilinx XC5VLX50 FPGA using four-neighbour connectivity with the possibility to scale up using a larger FPGA. The processor array operates at a frequency of 150 MHz and executes a peak of 153.6 GOPS (bitserial operations). Binary and 8-bit greyscale image processing is performed and demonstrated.

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Section: By the Dashed Lines)mentioning

confidence: 91%

Section: By the Dashed Lines)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A compact FPGA implementation of a bit-serial SIMD cellular processor array

Walsh

Dudek

2012

2012 13th International Workshop on Cellular Nanoscale Networks and Their Applications

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“…Over the last 25 years cellular nonlinear networks (CNN) [10] have proved to be suitable for high-speed image processing in numerous fields of application [6,27,28,38]. The concept of the CNN universal machine (CNN-UM) [31] evolves these networks to freely programmable and universal processors which-in contrast to numerous specialised image processing machines-are not limited to certain operations, but offer a broad selection of image processing operators and algorithms [18].…”

Section: Introductionmentioning

confidence: 99%

NEROvideo: a general-purpose CNN-UM video processing system

Müller

Tetzlaff

2014

J Real-Time Image Proc

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Emulations of cellular nonlinear networks (CNN) on digital reconfigurable hardware have proved to be adequate for highly-efficient computation of massive data, exceeding the accuracy and flexibility of full-custom designs. Based on a recently-proposed architecture for the emulation of a largescale CNN universal machine, a new real-time video processing system has been developed. Due to its free programmability and massively-parallel architecture the system is very suitable for high-speed computation of complex algorithms that follow the idea of spatio-temporal computing. Implemented on a stateof-the-art Xilinx Zynq system-on-chip, the proposed setup is capable of processing a 640 Â 480p video stream with up to 1,700 fps, depending on the respective algorithm.

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“…Many low-level vision problems can be solved efficiently by the use of pixel-per-processor cellular SIMD architectures [1], [2], [3], [4], [5]. But these cellular processor arrays lack fast long distance communication, as the cells are only connected in the nearest neighborhood.…”

Section: Introductionmentioning

confidence: 99%

Autonomous long distance transfer on SIMD cellular processor arrays

Geese

Dudek

2010

2010 12th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA 2010)

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Abstract-In image processing the tasks of rotating, mirroring and scaling the image are often required. These operations necessitate data transfer between distant elements in the image. SIMD processor arrays commonly support communication within the direct neighborhood only. In this paper a method for implementing long-distance data communication is proposed. Inspired by lattice gas cellular automata models and marching pixels, the developed method leads to an efficient pixel routing algorithm. Further, the use of autonomous elements leads to an emergent behavior that has been studied. Promising results for the above tasks have been achieved for simulations on nearestneighbor connected processor arrays.

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SIMD array on FPGA for B/W image processing

Cited by 6 publications

References 5 publications

A compact FPGA implementation of a bit-serial SIMD cellular processor array

A compact FPGA implementation of a bit-serial SIMD cellular processor array

NEROvideo: a general-purpose CNN-UM video processing system

Autonomous long distance transfer on SIMD cellular processor arrays

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