2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors 2012
DOI: 10.1109/asap.2012.8
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SIMD/MIMD Dynamically-Reconfigurable Architecture for High-Performance Embedded Vision Systems

Abstract: Image and video processing algorithms are becoming more and more sophisticated. An efficient hardware architecture is a requirement in order to address effectively the increasing computational workload. In a context of high performance, low cost and rapid prototyping, a hybrid SIMD/MIMD architecture for image processing is proposed in this work. By reusing functional units and including a dynamically reconfigurable datapath, this architecture enables high performance devices for general image processing tasks … Show more

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Cited by 13 publications
(4 citation statements)
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“…• An FPGA implementation of the architecture and the evaluation of the potential value of reconfigurable datapaths to face computer vision applications. This paper represents an extended version of [11]. Particularly, a more detailed description of the proposed architecture is included; new sections for instructions sets and scheduling are added; an extended section of performance evaluation and power consumption is presented; and a comparison with other architectures based on the computation of practical image processing algorithms is discussed.…”
Section: Contributionsmentioning
confidence: 99%
“…• An FPGA implementation of the architecture and the evaluation of the potential value of reconfigurable datapaths to face computer vision applications. This paper represents an extended version of [11]. Particularly, a more detailed description of the proposed architecture is included; new sections for instructions sets and scheduling are added; an extended section of performance evaluation and power consumption is presented; and a comparison with other architectures based on the computation of practical image processing algorithms is discussed.…”
Section: Contributionsmentioning
confidence: 99%
“…In addition, it aims to reduce the set-up time and ease algo-rithm migration by automatically managing tasks such as data I/O or synchronization between the computing units. The architectural details can be found in the work of Nieto et al [19]. Figure 4 depicts the main elements of the Image Coprocessor.…”
Section: Simd/mimd Dynamically-reconfigurable Architecturementioning
confidence: 99%
“…Clocked up to 150MHz, the peak performance is 19.6GOP/s and the maximum power consumption is 7.197W. More details of the hardware prototype are available in the article by Nieto et al [19]. The experimental architecture includes a basic linker and an assembler type programming interface.…”
Section: Accelerating Vision-based Applications With a Hybrid Reconfimentioning
confidence: 99%
“…With registers the core functionality can be multiplied through C-slow retiming concepts [10]. Thus, the number of registers preserved during reconfiguration of the register file is used to multiply the core functionality of the processor in a single die.…”
Section: Multiplying Core Functionalitymentioning
confidence: 99%