Similarity-index early seizure detector VLSI architecture

Abstract

A low power VLSI architecture implementing an algorithm for early seizure detection in epileptic patients using intracranial or scalp EEG data is proposed. The algorithm tested over more than 40 hours of recording from standard databases achieves a best-case result of 100% sensitivity at a false positive rate of 0.2 per hour. The algorithm is programmed on an FPGA and was experimentally validated along with a neural recording SoC chip to demonstrate a real-time seizure detection microsystem.