Simple Evaluation of the Nonlinearity Signature of  an ADC Using a Spectral Approach

Peralías, E.; Jalón, M. A.; Rueda, A.

doi:10.1155/2008/657207

Cited by 9 publications

(5 citation statements)

References 9 publications

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“…At the end of the test procedure, the obtained transfer function "g(y)" is used to compute the transfer function " f (x)". Such polynomials f (x) have been commonly used in the past to characterize the transfer function of ADCs [11], [19].…”

Section: Data Analysis and Mathematical Formulationmentioning

confidence: 99%

Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

Kook

Choi

Chatterjee

2013

IEEE Trans. VLSI Syst.

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A low-cost linearity test methodology for high-resolution analog-to-digital converters (ADCs) is presented in this paper. Linearity testing of ADCs requires high-precision digital-to-analog conversion (DAC) capability, commonly 3-bit higher resolution than the ADC under test. Further, a large number of ADC output data samples must be collected making conventional histogram testing impractical for high-resolution ADCs with 18-24 bit precision. In the proposed test methodology, two low-precision and low-cost DACs are used to generate a high-resolution ADC test stimulus. Significant reductions in test cost and test time are achieved by using low-cost instrumentation and by making fewer measurements than required for conventional histogram test. A least-squares-based polynomial fitting approach is used to determine the transfer function of the ADC under test. The generated transfer function is used to compute the non-linearity of the ADC accurately. No assumption is made regarding the linearity of the lower precision signal generators (DACs) used in the testing procedure. Software simulations and hardware experiments are performed to validate the proposed test methodology.Index Terms-Analog-to-digital converters (ADCs), automated test equipment (ATE), built-in-self-test (BIST), device under test (DUT), differential nonlinearity, digital-to-analog converters (DACs), integral nonlinearity.

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Section: Data Analysis and Mathematical Formulationmentioning

confidence: 99%

Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

Kook

Choi

Chatterjee

2013

IEEE Trans. VLSI Syst.

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“…The results indicate that surprisingly small amount of test data can be used to accurately predict INL of a 24bit ADC. The polynomialfitting based test is a popular method to characterize such transfer function of the system or ADCs [6], [11], [13]. However, a key question is whether these 4 code measurements are sufficient to predict all ADC anomalies induced by small and large process variations and parasitics.…”

Section: Iv2 Test With Reduced Number Of Codesmentioning

confidence: 99%

“…The approach builds a linear model in terms of code transition points and errors and measures only a defined subset of code transition levels. In addition, authors in [11]- [13] propose the nonlinearity testing of ADCs from spectral measurements, which are adequate for high-resolution ADC testing.…”

Section: Introductionmentioning

confidence: 99%

Optimal Linearity Testing of Sigma-Delta Based Incremental ADCs Using Restricted Code Measurements

Kook

Gomes

Jin

et al. 2011

2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop

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Linearity testing of high-precision (beyond 20-bit resolution) Analog-to-Digital converters (ADCs) is extremely expensive due to the large number of codes (>16 million for a 24-bit converter) that need to be tested and the associated low data rates making traditional histogram based testing infeasible. Industry often performs linearity test for such high-precision data converters with significantly reduced numbers of code measurements during production test. Given a specified allowed number of code measurements, the problem is to determine the requisite code points that result in the highest failure coverage. In this report, a methodology and tools for analyzing the "goodness" of a particular choice of test code points versus another is described. A least squares based polynomial fitting approach using measurements made at selected test code points is used to characterize the transfer function of the ADC for INL (Integral Nonlinearity) error. In addition, the characteristics of devices that may escape from the proposed approach (test escapes) are revealed for the specified test via an optimization based search technique. Software simulations are performed to study and validate the proposed methodology.

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“…Translating these constraints into accuracy figures, both mean at least two more resolution bits than that of the ADC to be tested. Some authors have been dealing either with the implementation of high resolution signals for on-chip testing [1][2][3][4] or with devising simpler measurement procedures [5].…”

Section: A Relaxing Input Requirementsmentioning

confidence: 99%

(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems

Barragán

Huertas

Rueda

et al. 2010

2010 Fifth IEEE International Symposium on Electronic Design, Test &Amp; Applications

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Simple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral Approach

Cited by 9 publications

References 9 publications

Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

Optimal Linearity Testing of Sigma-Delta Based Incremental ADCs Using Restricted Code Measurements

(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems

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