We introduced a high porosity ultralow-k film into a Cu damascene interconnect without increasing the dielectric constant ͑k͒ of a low-k film after interconnect formation. A high elastic modulus ͑9 GPa͒ with ultralow-k value ͑Ͻ2.1͒ was achieved by using a self-assembled porous silica film formed with UV irradiation and a silylation anneal. Performing the silylation anneal after trench etching results in recovery of the k value and dielectric properties. A sidewall protection process carried out before metalization protects the low-k film against process-induced damage. The time-dependent-dielectric breakdown lifetime is 10 years at a high electric field of 2.3 MV/cm.To reduce signal propagation delay and power consumption, the time constants of Cu interconnects in large-scale integrations ͑LSIs͒ must be improved, which can be achieved by using ultralow dielectric constant ͑k͒ interlayer dielectrics ͑ILDs͒ between the interconnects. Reducing the density of a dielectric material lowers the k value of the dielectric film. However, it also causes an unacceptable reduction of mechanical strength. Self-assembled porous silica ͑Po-SiO͒ is a promising material for forming low-k/Cu damascene interconnects with high porosity and high mechanical strength, which can be extended over several generations of technology nodes. [1][2][3][4] In this study, we introduced self-assembled Po-SiO into low-k/Cu damascene multilevel interconnects and investigate the feasibility of a low-k/Cu damascene process for 200 nm pitch multilevel interconnects with 65 nm node technology.
Comparison of Effective Dielectric ConstantsEffective k ͑k eff ͒ values of stacked ILD films for 100 nm pitch multilayered Cu damascene interconnects are shown in Fig. 1a. k eff is calculated by using a two-dimensional capacitance simulator ͑Maxwell͒. The calculation process was as follows: The parasitic capacitance of an electrode ͑line͒ of a sample interconnect structure was calculated by using the simulator and by fitting the capacitance of a monolithic dielectric ͑k = k eff ͒/Cu interconnect with changing k eff . Figure 1 shows the cross section of the compared Cu interconnect structures with the Po-SiO film as a line and via low-k layers and with an air gap as a line low-k layer. The air gap structure must be thick enough for the cap film to avoid unlanded via issues due to lithography misalignment. 5 For the air gap structure, only a high modulus dielectric can be used for the cap layer and via low-k layer, as shown in Fig. 1b and Table I. The k eff value using a conventional cap film ͑k = 3.0͒ and an etch-stop film ͑k = 4.0͒ can be reduced from 3.3 to 2.45 by applying an advanced Po-SiO film ͑k = 1.9͒, as shown in Fig. 1a. With a conventional k value and thick ͑45 nm͒ cap film, the k eff of the proposed air gap structures is 2.66. Therefore, the k eff value of the Po-SiO interconnect can be lower than that of the air gap interconnect if the same cap and etch-stop films are used.
ExperimentalA self-assembled scalable Po-SiO film was formed, followed by a Xe ...