SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration

Liu, Leibo; Wang, Dong; Yin, Shouyi; Chen, Yingjie Victor; Zhu, Min; Wei, Shaojun

doi:10.1109/tvlsi.2013.2295622

Cited by 23 publications

(9 citation statements)

References 18 publications

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“…After that, we get a series of parameter sets ( , η, II). Then for each ( , η, II), we can estimate the low bound of NLET (NLET − ) by (22). Based on these rough performance estimates, we use a two-phase search method to find the valid mapping.…”

Section: Efficient Solutionmentioning

confidence: 99%

“…When we have the search space of , η, II, we can estimate NLET − for each parameter set ( , η, II) by (22) and generate the NLET − series. Since NLET − is not a convex function due to the uncontinuity of ρ(m, e) in (19), we use the enhanced genetic algorithm (GA) proposed in [8] to facilitate the traversal of solution space of .…”

Section: N L E T − Series Generationmentioning

confidence: 99%

“…Then, for II ∈ [MII, ηII s ], we can estimate the lower bound of NLET (NLET − ) (line 18). After all η and II related to the matrix are traversed, the individuals in the next generation are generated by GA algorithm and the previous steps (lines [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22] are repeated. After the generation number exceeds the G max , we get the series of NLET − for all parameter sets ( , η, II).…”

Section: Nested Loop Pipelining Flowmentioning

confidence: 99%

“…The performance results are obtained from a cycle-accurate CGRA simulator [22]. The target CGRA has a homogeneous PEA coupled with an ARM7 host controller.…”

Section: A Experimental Setupmentioning

confidence: 99%

“…For both CGRAs, the architectural parameters are set to (σ = 2, γ = 1). The choice of these parameters is to avoid that the second term in (22) is reduced to zero so that the performance model can be comprehensively validated. We compare three pairs of metrics, N cs versus N cs *, N ld versus N * ld , and NLET − versus NLET * .…”

Section: B Validation Of Performance Modelmentioning

confidence: 99%

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Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures

Yin

Liu

Peng

et al. 2016

IEEE Trans. VLSI Syst.

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Coarse-grained reconfigurable architecture (CGRA) is a promising architecture with high performance, high power efficiency, and attraction of flexibility. The computation-intensive portions of applications, i.e., loops, are often implemented on CGRAs for acceleration. The loop pipelining techniques are usually used to exploit the parallelism of loops. However, for nested loops, the existing loop pipelining methods often result in poor hardware utilization and low execution performance. To tackle this problem, this paper makes three contributions: 1) we propose the use of affine transformation to facilitate nested loop pipelining; 2) based on polyhedral model, we present a precise and general formulation of the nested loop pipelining problem on a CGRA; and 3) using the insights from problem formulation, we design a joint affine transformation and multipipeline merging approach to improve the performance of nested loop on CGRA. The experimental results show that our approach can improve the performance of nested loops up to 35% on average, compared with the state-of-the-art techniques.

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Section: Efficient Solutionmentioning

confidence: 99%

Section: N L E T − Series Generationmentioning

confidence: 99%

Section: Nested Loop Pipelining Flowmentioning

confidence: 99%

“…The performance results are obtained from a cycle-accurate CGRA simulator [22]. The target CGRA has a homogeneous PEA coupled with an ARM7 host controller.…”

Section: A Experimental Setupmentioning

confidence: 99%

Section: B Validation Of Performance Modelmentioning

confidence: 99%

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