Simulated annealing search through general structure floorplans using sequence-pair

Kiyota, Koji; Fujiyoshi, Kunihiro

doi:10.1109/iscas.2000.856000

Cited by 20 publications

(12 citation statements)

References 8 publications

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“…Koji kiyota, Kunihiro fuiiyoshi (2000) [13] proposed a novel solution space of floorplans for simulated annealing (SA) which consists of the all general floorplans with exact n rooms, where n is the number of given modules, using sequence-pair. By using ingenious data structure, a feasible adjacent floorplan can be obtained in O(n2) time and the reachability from any floorplan to any other in the proposed solution space will be proved.…”

Section: Brief Literature Review Of Non-slicing Floorplansmentioning

confidence: 99%

Non Slicing Floorplan Representations in VLSI Floorplanning: A Summary

Jain¹,

Singh²

2013

IJCA

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Section: Brief Literature Review Of Non-slicing Floorplansmentioning

confidence: 99%

Non Slicing Floorplan Representations in VLSI Floorplanning: A Summary

Jain¹,

Singh²

2013

IJCA

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“…The representation should be able to traverse large search space in least computational time. The existing representations for non-slicing floorplans are Bounded Slicing Grid Structure (BSG) [19] [20], Corner Block List (CBL) [21], Corner Sequence (CS) [22], Sequence Pair (SP) [23] [24], B* Tree [25] [26], Transitive Closure Graph (TCG) [27] [28], Integer Coding [29], O Tree [30]. These representations can be compared based on solution space search and computational complexity as shown in Table 1.…”

Section: Representations For Non-slicing Floorplansmentioning

confidence: 99%

Early Layout Design Exploration in TSV-based 3D Integrated Circuits

Ahmed¹

2000

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Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage.The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% -12% compared to wirelength-aware cost function.ii The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance.Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and blocks, as well as nets-to-TSVs assignment to obtain floorplans with minimized coupling noise.We also suggested diagonal TSV arrangement for larger TSV pitch and nonuniform pitch arrangement for reducing worst TSV-to-TSV coupling, thereby minimizing the coupling noise in the interconnects.This thesis also focuses on more realistic evaluation and optimization of delay and power in TSV based 3D integrated circui...

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“…However, the slicing structure does not capture all floorplans. Sequence pairs (SPs) [3] were used for the packing problem [4], [5]. The bounded-sliceline grid (BSG) [6] is technically a floorplanning data structure as the number of nonzero-area rooms equals the number of modules.…”

Section: Introductionmentioning

confidence: 99%

The quarter-state-sequence floorplan representation

Sakanushi

Kajitani²,

Mehta³

2003

IEEE Trans. Circuits Syst. I

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A floorplan of a bounding box is its dissection into rectangles (rooms) by horizontal and vertical segments. This paper proposes a string data structure called the Quarter-state sequence (or Q sequence) to represent the floorplan. The Q sequence is a concatenation of the states of rooms along the Abe order and is related to the VH graph, which is the union of the vertical-constraint and horizontal-constraint graphs. It is proved that any floorplan of rooms is uniquely encoded by a Q sequence and any Q sequence is uniquely decoded to a floorplan, both in ( ) time. An exact formula for counting distinct floorplans is given and compared with existing bounds. A linear time transformation of one Q sequence to another is defined. An -room packing algorithm based on simulated annealing was implemented and found to compare favorably with existing packing algorithms.

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Simulated annealing search through general structure floorplans using sequence-pair

Cited by 20 publications

References 8 publications

Non Slicing Floorplan Representations in VLSI Floorplanning: A Summary

Non Slicing Floorplan Representations in VLSI Floorplanning: A Summary

Early Layout Design Exploration in TSV-based 3D Integrated Circuits

The quarter-state-sequence floorplan representation

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