Simulating Open-Via Defects

Spinner, S.; Jiang, Jie; Polian, Ilia; Engelke, Piet; Becker, Bernd

doi:10.1109/ats.2007.4388023

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2008

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“…We laid out ISCAS 85 circuits and extracted the parasitic coupling capacitances CC using the flow outlined in [18]. We applied our ATPG to the complete list of both inter-and intra-layer interconnect opens.…”

Section: Resultsmentioning

confidence: 99%

Automatic Test Pattern Generation for Interconnect Open Defects

Spinner

Polian

Engelke

et al. 2008

26th IEEE VLSI Test Symposium (Vts 2008)

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We present a fully automated flow to generate test patterns for interconnect open defects. Both inter-layer opens (openvia defects) and arbitrary intra-layer opens can be targeted. An aggressor-victim model used in industry is employed to describe the electrical behavior of the open defect. The flow is implemented using standard commercial tools for parameter extraction (PEX) and test generation (ATPG). A highly optimized branch-and bound algorithm to determine the values to be assigned to the aggressor lines is used to reduce both the ATPG efforts and the number of aborts.The resulting test sets are smaller and achieve a higher defect coverage than stuck-at n-detection test sets, and are robust against process variations.

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Section: Resultsmentioning

confidence: 99%