Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors

Abstract

In this paper, we extensively analyzed the drain-induced barrier lowering (DIBL) and leakage current characteristics of the proposed partial isolation field-effect transistor (PiFET) structure. We then compared the PiFET with the conventional planar metal-oxide semiconductor field-effect transistor (MOSFET) and silicon on insulator (SOI) structures, even though they have the same doping profile. Two major features of the PiFET are potential condensation and potential modulation by a buried insulator. The potential modulation near the drain region can control the electric field in the overlapped region of the drain and gate, because it causes a high gate-fringing field. Therefore, we suggest guidelines with respect to the optimal PiFET structure.

Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

“…In this paper, we proposed a new device with a partial isolation region under the storage node of conventional S-FinFET. This structure can be fabricated by using an isotropic dry etching technique for the buried insulator under the cell transistor [7,8]. We analyzed electrical characteristics of this proposed device and compared them with those of conventional S-FinFETs of the same size.…”

“…The proposed FinFET exhibited four times lower I off than modified S-FinFET, called RFinFET, with more improved drain-induced barrier lowering (DIBL) characteristics, while minimizing I on reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved drain-induced barrier lowering (DIBL) and I off characteristics as gate channel length decreased.Keywords: gate-induced drain leakage (GIDL); drain-induced barrier lowering (DIBL); recessed channel array transistor (RCAT); on-current (I on ); off-current (I off ); subthreshold slope (SS); threshold voltage (V TH ); saddle FinFET (S-FinFET); potential drop width (PDW); shallow trench isolation (STI); technique for the buried insulator under the cell transistor [7,8]. We analyzed electrical characteristics of this proposed device and compared them with those of conventional S-FinFETs of the same size.…”

“…Keywords: gate-induced drain leakage (GIDL); drain-induced barrier lowering (DIBL); recessed channel array transistor (RCAT); on-current (I on ); off-current (I off ); subthreshold slope (SS); threshold voltage (V TH ); saddle FinFET (S-FinFET); potential drop width (PDW); shallow trench isolation (STI); technique for the buried insulator under the cell transistor [7,8]. We analyzed electrical characteristics of this proposed device and compared them with those of conventional S-FinFETs of the same size.…”

Nanoelectronic Materials, Devices and Modeling: Current Research Trends

“…This issue collected two approaches to achieve a steep SS: (1) using the insulator-metal phase transition of VO 2 to achieve a decent SS of 42 mV/dec [6]; (2) using an L-shaped tunneling FET to improve the SS [7]. In addition, the drain-induced barrier lowering (DIBL) effect and leakage of a partial isolation FET for sub-0.1 µm have been studied [8].…”

S-TAT Leakage Current in Partial Isolation Type Saddle-FinFET (Pi-FinFET)s

“…To address this issue, Pi-FinFETs (Pi-SFinFET, Pi-RFinFET) that have a partial isolation region under the storage node of S-FinFETs (SFinFET, RFinFET) have been proposed [12][13][14]. However, in Pi-FinFETs fabricated using an isotropic dry etching technique where the insulator is buried under the cell transistor [15,16], the buried insulator can cause an interface trap between itself and the drain region [17]. Consequently, this can have an adverse effect on leakage current.…”