Simulation and modelling of VDMOSFET self protection under TLP-stress

Sauter, Martin; Willemen, Joost

doi:10.1016/j.microrel.2009.10.007

Cited by 2 publications

(1 citation statement)

References 15 publications

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“…However, a VDMOS is commonly used in high voltage applications, therefore, the issue of ESD damage, or device degradation and ESD protection should be considerable attention as well. Unfortunately, many ESD protection studies and efforts are focused on the VLSI era; seldom literatures are cared about this VDMOS topic [13].…”

Section: Introductionmentioning

confidence: 99%

ESD Failure Analysis and Robustness Design in Vertical-Diffused MOS Transistors

Chen

Lee

Chu

2014

AMR

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This paper deals with a detailed study of ESD failure mode and how to strengthen of the VDMOS used for power applications. The ESD post-zapped failure of power VDMOS transistors due to HBM, MM, and CDM stresses are examined in this work. Through standard failure analysis techniques by using EMMI and SEM were applied to identify the failure locations. The MM failure mode in this power MOSFET was caused by the gate oxide breakdown near n+ region in the source end as an ESD zapping. And, the ESD failure damage under HBM and CDM stresses were caused by the gate material molten near the gate pad and tunneled through the oxide layer into silicon epitaxial layer. Furthermore, the ESD robustness designs of power VDMOS transistors are also addressed in this work. The first ESD incorporated design is Zener diodes back-to-back clamping the gate-to-source pad, and on the other hand, another one excellent design contains two Zener diodes clamping the gate-to-source and gate-to-drain terminals of a VDMOS, respectively.

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Section: Introductionmentioning

confidence: 99%