Simulation and synthesis of networks-on-chip by using NoCSimp HDL library

Romanov, A. Yu.; Ivannikov, Alexander; Romanova, I. I.

doi:10.1109/elnano.2016.7493072

Cited by 9 publications

(2 citation statements)

References 7 publications

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“…Testing was performed on the two routers: based on a router from the Netmaker [28] library implementing all the main technical solutions used in NoCs (wormhole routing, QoS arbitration, etc. ), and on simplified routers from the NoCSimp library [34]. In addition, the modules, generating connections between routers to support the synthesis of circulant topologies, were modified.…”

Section: Methodsmentioning

confidence: 99%

Development of routing algorithms in networks-on-chip based on ring circulant topologies

Romanov

2019

Heliyon

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This work is devoted to the study of communication subsystem of networks-on-chip (NoCs) development with an emphasis on their topologies. The main characteristics of NoC topologies and the routing problem in NoCs with various topologies are considered. It is proposed to use two-dimensional circulant topologies for NoC design, since they have significantly better characteristics than most common mesh and torus topologies, and, in contrast to many other approaches to improving topologies, have a regular structure. The emphasis is on using ring circulants which although in some cases have somewhat worse characteristics than the optimal circulants, compensate by one-length first generatrix in such graphs that greatly facilitate routing in them. The paper considers three different approaches to routing in NoCs with ring circulant topology: Table routing, Clockwise routing, and Adaptive routing. The algorithms of routing are proposed, the results of synthesis of routers, based on them, are presented, and the cost of chip resources for the implementation of such communication subsystems in NoCs is estimated.

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Section: Methodsmentioning

confidence: 99%

Development of routing algorithms in networks-on-chip based on ring circulant topologies

Romanov

2019

Heliyon

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“…To debug a digital system design we need the finite length test set TST n  F n , the power of TST n has to be finite. And then we need to run all test of TST n on (L 1 , L 2 , …, L n ), to check if the results are correct, if any result is not correct then to localize and correct the error [8,9].…”

Section: Structural Vertical Decompositionmentioning

confidence: 99%

Principals of digital system design debugging decomposition

Ivannikov

2022

J. Phys.: Conf. Ser.

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Up-to-date digital integrated circuits become more and more complicated. The amount of its elements increases enormously, sizes of the elements become very small. That is why the task of digital system design debugging becomes more and more complicated. So, digital system design debugging decomposition is required. In the paper design debugging decomposition by simulation is considered. The classification of debugging decomposition methods and its algebraic models are presented. The following decomposition methods are described: vertical and horizontal structure decomposition, functional decomposition, decomposition based on error types.

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