Simulation-based analysis of FF behavior in presence of power supply noise

Miura, Yoshio; Yamamoto, Takuya

doi:10.1109/iolts.2017.8046211

Cited by 2 publications

(1 citation statement)

References 11 publications

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“…A well-known fact is that there is a trade-off between having a low quiescent current and a transient response or power supply ripple reduction, which were the motivations of past studies. The transient response degradation causes MCU to malfunction [3], [4]; thus, it is recognized as a significant characteristic of power management IC. The fast current slew rate (SR) to the gate of the pass transistor realizes a fast settling time and small undershoot and overshoot.…”

Section: Introductionmentioning

confidence: 99%

Ultra-Low Quiescent Current LDO with FVF-Based Load Transient Enhanced Circuit

Mii

Nagahama

Watanabe

2020

IEICE Trans. Electron.

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This paper proposes an ultra-low quiescent current lowdropout regulator (LDO) with a flipped voltage follower (FVF)-based load transient enhanced circuit for wireless sensor network (WSN). Some characteristics of an FVF are low output impedance, low voltage operation, and simple circuit configuration [1]. In this paper, we focus on the characteristics of low output impedance and low quiescent current. A load transient enhanced circuit based on an FVF circuit configuration for an LDO was designed in this study. The proposed LDO, including the new circuit, was fabricated in a 0.6 μm CMOS process. The designed LDO achieved an undershoot of 75 mV under experimental conditions of a large load transient of 100 μA to 10 mA and a current slew rate (SR) of 1 μs. The quiescent current consumed by the LDO at no load operation was 204 nA.

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Section: Introductionmentioning

confidence: 99%