Simulation based post OPC verification to enhance process window, critical failure analysis, and yield

Kang, Ji-Hoon; Choi, Jaeyoung; Yun, Kyunghee; Do, Munho; Lee, Yong-Suk; Kim, Keeho

doi:10.1117/12.657050

Cited by 5 publications

(2 citation statements)

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“…Verification of lithographic errors is further complicated when the process window (pw) is simulated 3 . In this case, simulated errors at focus and dose deviations from nominal are tabulated.…”

Section: Nomentioning

confidence: 99%

Intelligent visualization of lithography violations

Ziger

2007

SPIE Proceedings

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Section: Nomentioning

confidence: 99%

Intelligent visualization of lithography violations

Ziger

2007

SPIE Proceedings

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“…Therefore OPC verification has become more important technique than OPC itself. [1][2][3][4][5][6] In this paper, for more accurate and efficient OPC verification, we introduce various CD error non-checking areas with different corner length. First, we will classify available sizes of various non-checking area for KrF Cu damascene process, when the allowable CD error for one side edge is smaller than 3nm, 5nm and 7nm, respectively.…”

Section: Introductionmentioning

confidence: 99%

The study for increasing efficiency of OPC verification by reducing false errors from bending pattern by using different size of CD error non-checking area with various corner lengths

Lee

Kim

et al. 2007

SPIE Proceedings

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In recent years, model based verification for optical proximity effect correction (OPC) has become one of the most important items in semiconductor industry. Major EDA companies have released various softwares for OPC verification. They have continuously developed and introduced new methods to achieve more accurate results of OPC verification. The way to detect only real errors by excluding false errors is the most important thing for accurate and fast verification process, because more time and human resource are needed to inspect the result of verification as increasing false errors. A major source of false errors is bending patterns. The number of those from bending patterns is over thousands and they are inevitable. The most verification tools have the scheme for excluding those by using CD error non-checking or filtering area. Real errors around bending pattern will not be able to detect with too big size of area, while too many false error will be reported with too small size of area. Since currently most verification tools had only a fixed area size for filtering, it has been impossible to achieve most accurate and efficient verification results. Through the optimization of area size with different corner length, we could get more accurate and efficient results and decrease the time for review to find real errors. In this paper, the suggestion in order to increase efficiency of OPC verification process by using different size of CD error non-checking area with various corner lengths is presented.

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Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house’s approach

Wang

et al. 2007

J. Micro/Nanolith. MEMS MOEMS

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We describe design house approaches for design rule developments with emphasis of valuations of pre-optical proximity correction ͑pre-OPC͒ layouts and their simulation results. To begin, we describe the procedure of the simulation model calibration. An evaluation of metrics for analyzing the design layouts is then described. Due to the unavailability of post-OPC layouts, both pre-OPC and trial-OPC simulations are studied. A range of layout pattern density, within which the pre-OPC metric follows the post-OPC's, is estimated. Within this pattern density range, pre-OPC layout then can be evaluated to identify potential process "hot spots." With this approach, a set of design for manufacturability ͑DFM͒ compliance design rules is derived and applied to the product developments for both 90-and 65-nm process technology nodes. Several hot spots in the products ͑designed with 90-nm design rules͒ are located and fixed using layout optimization guided by the DFM rules. Simulated image contours and in-line scanning electron microscope ͑SEM͒ images validate the approach. © 2007 Society of Photo-Optical Instrumentation Engineers.

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Simulation based post OPC verification to enhance process window, critical failure analysis, and yield

Cited by 5 publications

References 0 publications

Intelligent visualization of lithography violations

Intelligent visualization of lithography violations

The study for increasing efficiency of OPC verification by reducing false errors from bending pattern by using different size of CD error non-checking area with various corner lengths

Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house’s approach

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