Simulation Methodology for Electron Transfer in CMOS Quantum Dots

Sokolov, Andrii; Mishagli, Dmytro; Giounanlis, Panagiotis; Bashir, Imran; Leipold, Dirk; Koskin, Eugene; Staszewski, Robert Bogdan; Blokhina, Elena

doi:10.1007/978-3-030-50433-5_50

Cited by 6 publications

(10 citation statements)

References 25 publications

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“…Fig. 1 presents an overview of the CMOS position-based charge qubit structure containing an array of QDs [9], [11], [12], with schematics of nearby interfacing circuitry: reset, control, singleelectron injector, and detector. It is part of a quantum processor implemented in 22-nm FDSOI CMOS and operating at cryogenic temperature of 3.4 K, whose earlier version was presented in [10].…”

Section: A Imposer/injector Topologymentioning

confidence: 99%

“…Table I summarizes the key specifications for the CDAC in the proposed system. The values are derived from physical equations and COMSOL multiphysics modeling of the QDA structures [9], [11]. To overcome the kT/q thermal energy of an electron, the LSB voltage step (i.e., resolution) at the tunnel junction between QDs should be finer than 300 µV at 4 K. However, the voltage applied at the imposer gates should be ∼10× larger due to the capacitive division between C ox (gate oxide capacitance) and C t (tunnel junction capacitance).…”

Section: A Imposer/injector Topologymentioning

confidence: 99%

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A Fully Integrated DAC for CMOS Position-Based Charge Qubits with Single-Electron Detector Loopback Testing

Esmailiyan¹,

Wang

Asker³

et al. 2020

IEEE Solid-State Circuits Lett.

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This letter presents a fully integrated interface circuitry with a position-based charge qubit structure implemented in 22-nm FDSOI CMOS. The quantum structure is controlled by a tiny capacitive DAC (CDAC) that occupies 3.5×45 µm 2 and consumes 0.27 mW running at a 2-GHz system clock. The state of the quantum structure is measured by a single-electron detector that consumes 1 mW (including its output driver) with an area of 40×25 µm 2 . The low power and miniaturized layout of these circuits pave the way for integration in a large quantum core with thousands of qubits, which is a necessity for practical quantum computers. The CDAC output noise of 12 µV-rms is estimated through mathematical analysis while the ≤ 0.225 mV-rms input referred noise of the detector is verified by measurements at 3.4 K. The functionality of the system and performance of the CDAC are verified in a loopback mode with the detector sensing the CDAC-induced electron tunneling from the floating diffusion node into the quantum structure.

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Section: A Imposer/injector Topologymentioning

confidence: 99%

Section: A Imposer/injector Topologymentioning

confidence: 99%

A Fully Integrated DAC for CMOS Position-Based Charge Qubits with Single-Electron Detector Loopback Testing

Esmailiyan¹,

Wang

Asker³

et al. 2020

IEEE Solid-State Circuits Lett.

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“…The currently estimated decoherence time in our system is >50 ns [56], which is 2-3 orders of magnitude shorter than that of the spin-based qubits. However, the cut-off frequency (f T ) of the used process technology is in the hundreds of GHz, allowing realization of quantum gate flip operations <50 ps, which is 2-3 orders of magnitude faster than with the spin counterparts.…”

Section: Qubit Interface Circuitrymentioning

confidence: 82%

“…2) allows the individual electrons to travel within the structure [7], [8]. For example, once the electron is injected into a QD, it can be transported to a neighbor QD through a π phase shift [56]. It can then be transported to next QD through another π phase shift.…”

Section: Overview Of Qda Structure For Charge Qubitsmentioning

confidence: 99%

“…Key specifications of the CDAC for the designed system are summarized in Table I. They are derived from physical equations and COMSOL multi-physics modeling of the QD array structure [8], [56]. To achieve the required signal-tonoise ratio compared with the kT /q thermal energy of an electron, the resolution of the voltage step at the tunnel junction between QDs should be smaller than 300 µV at 4 K. Yet, the capacitive division between C ox (gate oxide capacitance) and C t (tunnel junction capacitance), necessitates the voltage levels presented at the imposer gates to be ∼10× larger.…”

Section: B Imposer and Injector Topology 1) Circuit Implementationmentioning

confidence: 99%

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Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC

Staszewski

Esmailiyan²,

Wang

et al. 2022

IEEE Open J. Solid-State Circuits Soc.

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We present a fully integrated cryogenic controller for electrostatically controlled quantum dots (QDs) implemented in a commercial 22-nm FD-SOI CMOS process and operating in a quantum regime. The QDs are realized in local well areas of transistors separated by tunnel barriers controlled by voltages applied to gate terminals. The QD arrays (QDA) are co-located with the control circuitry inside each quantum experiment cell, with a total of 28 of such cells comprising this system-on-chip (SoC). The QDA structure is controlled by small capacitive digital-to-analog converters (CDACs) and its quantum state is measured by a single-electron detector.The SoC operates at a cryogenic temperature of 3.4 K. The occupied area of each QD array is 0.7×0.4 µm 2 , while each QD occupies only 20×80 nm 2 . The low power and miniaturized area of these circuits are an important step on the way for integration of a large quantum core with millions of QDs, required for practical quantum computers. The performance and functionality of the CDAC are validated in a loop-back mode with the detector sensing the CDAC-compelled electron tunneling from the quantum point contact (QPC) node into the quantum structure. Position of the injected charge inside the QD array is intended to be controlled through the CDAC codes and programmable pulse width. Quantum effects are shown by an experimental characterization of charge injection and quantization into the QD array consisting of three coupled QDs. The charge can be transferred to a QD and sensed at the QPC, and this process is controlled by the relevant voltages and CDACs.Index Terms-Capacitive DAC (CDAC), charge qubits, cryo-CMOS, fully depleted silicon-on-insulator (FD-SOI), imposer, positionbased qubits, quantum computer (QC), quantum dot (QD), single-electron detector, single-electron injector. I. INTRODUCTIONQ UANTUM computing is a new paradigm that utilizes the fundamental principles of quantum mechanics, such as superposition, interference and entanglement [1], [2]. The range of complex problems from mathematics, chemistry and material science that could be solved with quantum computing is far beyond the reach of today's most powerful supercomputers. The potential is thus immense. Quantum bits (qubits), basic units of quantum information, operate at a molecular/atomic level. They are extremely fragile and difficult to manipulate and read out. Some quantum computer technologies, such as based on trapped ions and photons, do not require the equipment to be cryogenically cooled [3], [4], but the majority of qubits must operate under extremely low Manuscript received

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CMOS charge qubits and qudits: entanglement entropy and mutual information as an optimization method to construct CNOT and SWAP Gates

Giounanlis

Sokolov

et al. 2021

Semicond. Sci. Technol.

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In this paper, we propose an optimization method for the construction of two-qubit and two-qudit quantum gates based on semiconductor position-based charge qubits. To describe the evolution of various quantum states, we use a Hubbard based model and Lindblad formalism. The suggested optimization algorithm uses the time evolution of entanglement entropy and mutual information for the determination of the system parameters to achieve high fidelity gates.

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Simulation Methodology for Electron Transfer in CMOS Quantum Dots

Cited by 6 publications

References 25 publications

A Fully Integrated DAC for CMOS Position-Based Charge Qubits with Single-Electron Detector Loopback Testing

A Fully Integrated DAC for CMOS Position-Based Charge Qubits with Single-Electron Detector Loopback Testing

Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC

CMOS charge qubits and qudits: entanglement entropy and mutual information as an optimization method to construct CNOT and SWAP Gates

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