Simulation of 2D Layered Material Ballistic FETs using a Hybrid Methodology

Pon, Adhithan; Carmel, Santhia; Bhattacharyya, Arkaprava; Rathinam, Ramesh

doi:10.1109/edssc.2019.8754400

Cited by 5 publications

(3 citation statements)

References 9 publications

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“…[105][106][107] Our research group developed a new method (hybrid) that includes both DFT and technology computer-aided design (TCAD) tools to simulate the phosphorene-based FET device characteristics. 108,109 The overall methodology consists of two sections: (1) computation of the phosphorene layer electrical parameters using DFT and the Quantumwise tool; and (2) incorporating the electrical parameters into device simulation using TCAD. The detailed methodology flow is shown in Fig.…”

Section: Hybrid Methodsmentioning

confidence: 99%

Recent Developments in Black Phosphorous Transistors: A Review

Pon

Bhattacharyya

Rathinam

2021

J. Electron. Mater.

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Two-dimensional (2D) materials like graphene, phosphorene, germanene, silicene, and transition metal dichalcogenides have attracted intense research attention because of their rich physics and potential for integration into next-generation electronic devices. These materials offer superior electrostatic control to their bulk counterparts, which makes them fascinating for device fabrication. After graphene and MoS 2 , the most intensively explored 2D material is black phosphorus (BP). During the past half-decade, BP has notably achieved excellent performance when included in transistors. This review paper aims to throw some light on BP properties and their performance in a field effect transistor device. The state-of-the-art BP transistors are reviewed, and a balanced view of both the benefits and drawbacks is provided. Keywords 2D material • black phosphorous • phosphorene • TCAD • DFT • MOSFET • TFET* Ramesh Rathinam

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Section: Hybrid Methodsmentioning

confidence: 99%

Recent Developments in Black Phosphorous Transistors: A Review

Pon

Bhattacharyya

Rathinam

2021

J. Electron. Mater.

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“…The total gate capacitance (

C_{t}

) is

false[1 / C_{t} = 1 / C_{ox} + 1 / C_{Q} false]

. It is a series combination of gate oxide capacitance (

C_{ox}

) and quantum capacitance (

C_{Q}

) [26, 27]. The high‐frequency characteristics of BP‐DGMOSFET are obtained by including the total gate capacitance (

C_{t}

).…”

Section: Methodsmentioning

confidence: 99%

Analysis of black phosphorus double gate MOSFET using hybrid method for analogue/RF application

Rathinam

Pon

Carmel

et al. 2020

IET Circuits, Devices & Systems

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“…Drift-Diffusion [18] model which takes into account the contribution of electron affinity, the band gap as well as the spatial variations of the electrostatic potential, is used to describe the current densities for electrons and holes. Since pure drift-diffusion model is not accurate enough beyond nanometers [19], and ballistic transport effects must be considered, we also incorporated ballistic mobility models [20], [21]. Because the oxide thickness and channel width have reached quantum-mechanical length scales, the wave nature of electrons and holes can no longer be neglected, thus Density-Gradient [22] is used to simulate quantization effects.…”

Section: B Simulation Physical Models and Calibrationmentioning

confidence: 99%

A Simulation Study of Gate-All-Around Nanowire Transistor With a Core-Substrate

2020

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In this letter, a novel Core-Substrate Gate-All-Around (CSGAA) nanowire structure has been proposed, investigated and simulated systematically based on 3D numerical simulation. This new structure is characterized by a Core-Substrate directly connected to the substrate wafer or well which is formed by a bulk region inside the tubular channel. Comparisons are carried out between conventional Gate-All-Around (GAA) nanowire transistor and newly proposed CSGAA structure. This budding structure exhibits a maximum of four orders of magnitude of reduction in off-state current, high saturation current and low performance degradation. With the help of Core-Substrate, the CSGAA structure is able to maintain excellent performance despite geometric and structural variation. Its special structure is very suitable for the use of vertical Gate-All-Around nanowire structure, making it a promising candidate of future high performance and low power CMOS devices. INDEX TERMS CMOS, core-substrate gate-all-around, CSGAA, field effect transistor, GAA, nanowire.

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Simulation of 2D Layered Material Ballistic FETs using a Hybrid Methodology

Cited by 5 publications

References 9 publications

Recent Developments in Black Phosphorous Transistors: A Review

Recent Developments in Black Phosphorous Transistors: A Review

Analysis of black phosphorus double gate MOSFET using hybrid method for analogue/RF application

A Simulation Study of Gate-All-Around Nanowire Transistor With a Core-Substrate

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