Simulation of switching noise in on-chip power distribution networks of FPGAs

Lalgudi, S.N.; Kretchmer, Yaron; Swaminathan, Madhavan

doi:10.1109/epep.2005.1563769

Cited by 5 publications

(4 citation statements)

References 5 publications

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“…While the spatial distribution of dynamic power consumption can usually be estimated at design time, or in some cases at runtime using performance counters, it is often not known how the dynamic power maps to IR drop. With FPGA-based systems, the power grid has irregularities and discontinuities [Lalgudi et al 2005], and the details are proprietary, preventing accurate simulation. Moreover, with certain systems even the dynamic power profile may not be well understood, due to changes in workload or autonomously generated configurations.…”

Section: Switching-induced Ir Dropmentioning

confidence: 99%

Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems

Zick

Hayes

2012

ACM Trans. Reconfigurable Technol. Syst.

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Electronic systems on a chip increasingly suffer from component variation, voltage noise, thermal hotspots, and other subtle physical phenomena. Systems with reconfigurability have unique opportunities for adapting to such effects. Required, however, are low-cost, fine-grained methods for sensing physical parameters. This article presents powerful, novel approaches to online sensing, including methods for designing compact reconfigurable sensors, low-cost threshold detection, and several enhanced measurement procedures. Together, the approaches help enable systems to autonomously uncover a wealth of physical information. A highly efficient counter and improved ring oscillator are introduced, enabling an entire sensor node in just 8 Virtex-5 LUTs. We describe how variations can be measured in delay, temperature, switching-induced IR drop, and leakage-induced IR drop. We demonstrate the proposed approach with an experimental system based on a Virtex-5, instrumented with over 100 sensors at an overhead of only 1.3%. Results from thermally controlled experiments provide some surprising insights and illustrate the utility of the approach. Online sensing can help open the door to physically adaptive computing, including fine-grained power, reliability, and health management schemes for systems on a chip. ACM Reference Format:Zick, K. M. and Hayes, J. P. 2012. Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems.

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Section: Switching-induced Ir Dropmentioning

confidence: 99%

Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems

Zick

Hayes

2012

ACM Trans. Reconfigurable Technol. Syst.

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“…As transistor feature sizes scale down into the nano-regime, cmos circuits become increasingly susceptible to error due to noise [6,8,24,25]. Judging by itrs projections for future supply voltages and thermal, switching, and cross-talk noise levels projected to be present, the noise to signal ratio (nsr)-previously defined by Cheemalavagu et.…”

Section: Future Technologies and Noisementioning

confidence: 99%

“…al [26]will be high enough to cause significant errors by 2016 [9]. For example, switching noise, also known as power supply noise, is as high as 30mV [6] in current technology. Furthermore, as studied by Elgamel [25], cross talk can be as high as 1.4V when power and ground lines are not used to shield interconnect.…”

Section: Future Technologies and Noisementioning

confidence: 99%

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Probabilistic arithmetic and energy efficient embedded signal processing

George

Marr

Akgul

et al. 2006

Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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Probabilistic arithmetic, where the i th output bit of addition and multiplication is correct with a probability pi, is shown to be a vehicle for realizing extremely energy-efficient, embedded computing. Specifically, probabilistic adders and multipliers, realized using elements such as gates that are in turn probabilistic, are shown to form a natural basis for primitives in the signal processing (dsp) domain. In this paper, we show that probabilistic arithmetic can be used to compute the fft in an extremely energy-efficient manner, yielding energy savings of over 5.6X in the context of the widely used synthetic aperture radar (sar) application [1]. Our results are derived using novel probabilistic cmos (pcmos) technology, characterized and applied in the past to realize ultra-efficient architectures for probabilistic applications [2,3,4]. When applied to the dsp domain, the resulting error in the output of a probabilistic arithmetic primitive, such as an adder for example, manifests as degradation in the signal-to-noise ratio (snr) of the sar image that is reconstructed through the fft algorithm. In return for this degradation that is enabled by our probabilistic arithmetic primitives -degradation visually indistinguishable from an image reconstructed using conventional deterministic approaches -significant energy savings and performance gains are shown to be possible per unit of snr degradation. These savings stem from a novel method of voltage scaling, which we refer to as biased voltage scaling (or bivos), that is the major technical innovation on which our probabilistic designs are based.

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Fast transient simulation algorithm for a 3D power distribution bus

Ahmad

Kanth

Chen

et al. 2010

2nd Asia Symposium on Quality Electronic Design (ASQED)

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Extensive transient simulations for on-chip power delivery networks are required to analyze power delivery fluctuations caused by dynamic IR and Ldi/dt drops. Speed and memory has become a bottleneck for simulation of power distribution networks in modern VLSI design where clock frequency is of the order of GHz. The traditional SPICE based tools are very slow and consume a lot of memory during simulation. The problem is further aggravated for huge networks like power distribution network within a stack of ICs inter-connected through TSVs. This type of 3D power distribution network may contain billions of nodes at a time. In this paper we proposed a faster transient simulation algorithm using visual C++. First we reduce 3D power distribution bus containing n nodes to a two terminal π network. Then we solve this two terminal reduced network for voltages and currents. After this, we apply back solving algorithm to the network to solve it for each of the intermediate nodes using visual C++. The proposed algorithm is quite accurate with 1-2% error when compared with Ansoft Nexxim4.1. The proposed algorithm is several times faster than Ansoft Nexxim as well as consumes significantly less memory as compared to Nexxim.

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Simulation of switching noise in on-chip power distribution networks of FPGAs

Cited by 5 publications

References 5 publications

Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems

Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems

Probabilistic arithmetic and energy efficient embedded signal processing

Fast transient simulation algorithm for a 3D power distribution bus

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