Simulation on endurance characteristic of charge trapping memory

Lun, Zhiyuan; Wang, Taihuan; Zeng, Lang; Zhao, Kai; Liu, Xiaoyan; Wang, Yi; Kang, Jinfeng; Du, Gang

doi:10.1109/sispad.2013.6650632

Cited by 7 publications

(5 citation statements)

References 13 publications

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“…Nevertheless, for the DP-HfO2 CTM device, an overall shift of VFB in the negative direction was observed. Based on previous studies, this is believed to be owing to the generation of a fixed oxide charge inside the unstable Hf-silicate interfacial layer of the DP-HfO2 CTM device by the P/E cycling, overall decreasing the VFB [52]. This shift in VFB can cause a cycling-dependent decrease in the reliability of the device during real-world memory operation and should be maximally suppressed [53].…”

Section: Resultsmentioning

confidence: 98%

Preparation of Remote Plasma Atomic Layer-Deposited HfO2 Thin Films with High Charge Trapping Densities and Their Application in Nonvolatile Memory Devices

Yoo¹,

Park²,

Kim³

et al. 2023

Nanomaterials

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Optimization of equipment structure and process conditions is essential to obtain thin films with the required properties, such as film thickness, trapped charge density, leakage current, and memory characteristics, that ensure reliability of the corresponding device. In this study, we fabricated metal–insulator–semiconductor (MIS) structure capacitors using HfO2 thin films separately deposited by remote plasma (RP) atomic layer deposition (ALD) and direct-plasma (DP) ALD and determined the optimal process temperature by measuring the leakage current and breakdown strength as functions of process temperature. Additionally, we analyzed the effects of the plasma application method on the charge trapping properties of HfO2 thin films and properties of the interface between Si and HfO2. Subsequently, we synthesized charge-trapping memory (CTM) devices utilizing the deposited thin films as charge-trapping layers (CTLs) and evaluated their memory properties. The results indicated excellent memory window characteristics of the RP-HfO2 MIS capacitors compared to those of the DP-HfO2 MIS capacitors. Moreover, the memory characteristics of the RP-HfO2 CTM devices were outstanding as compared to those of the DP-HfO2 CTM devices. In conclusion, the methodology proposed herein can be useful for future implementations of multiple levels of charge-storage nonvolatile memories or synaptic devices that require many states.

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Section: Resultsmentioning

confidence: 98%

Preparation of Remote Plasma Atomic Layer-Deposited HfO2 Thin Films with High Charge Trapping Densities and Their Application in Nonvolatile Memory Devices

Yoo¹,

Park²,

Kim³

et al. 2023

Nanomaterials

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“…Especially, program V th distribution can be distorted by ISPP noise [19], [20], WL-WL interference [22], and RTN effect of tunneling oxide and Poly-Si [23], [24], thus, the electron numbers in the nitride layer for a page memory cells are variable. Figure 4 shows the simulated single cell V th shift with different initial V th 4.5V, 4.7V, and 5.0V, respectively, where a self-consistent simulator (takes into consideration the tunneling processes, charge trapping/de-trapping mechanisms, and drift-diffusion transport within the storage layer) is used to simulate the program, erase, retention, and read operations as calibrated and verified in our previous works [25]- [27]. From the figure we can find that the retention V th distribution width decreases gradually, this is because of larger degradation rate for larger initial electron numbers in nitride layer, just like adding a negative variance noise (σ 2 ENF < 0) to initial program V th distribution.…”

Section: Retention Characteristicsmentioning

confidence: 99%

Investigation of Retention Noise for 3-D TLC NAND Flash Memory

Wang

Lun³

et al. 2019

IEEE J. Electron Devices Soc.

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In this paper, the retention noise [electron emission statistics (EES)] after program operation of 3-D triple-level program cell (TLC) NAND flash memory is investigated. Three main noise sources, consisting of essential EES (EEES), electron numbers fluctuation, and device parameters fluctuation to broaden the retention V th distributions are comprehensively considered, and the corresponding analytic models are developed. The impact of device parameters fluctuation is relatively larger than EEES and electron numbers fluctuation for our measured 3-D TLC NAND flash memory devices. Using the proposed models, the calculated V th distributions after different data retention times have good agreements with the measurements, which validate our proposed models. This paper provides a method to predict the V th distributions accurately and efficiently, and can help in improving reliability of 3-D TLC and quad-level program cell NAND flash memory. INDEX TERMS Retention V th distribution, retention noise, 3-D TLC NAND flash memory, reliability.

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“…Figure 5plots the ISPP program result of the single memory cell, where a self-consistent simulator is used to simulate the program, erase, retention, and read operations, as verified and calibrated in our previous studies[24][25][26][27]. The figure indicates that the ISPPInitialize Vth of every cell in a block (Gauss distribution, =−3, =0.21) Program WL j ; j=255 Adding ISPP noise (Poisson distribution, related with Vstep and device parameters) No Adding RTN effect (related with P/E cycling and temperature) Flowchart of the array program Vth distribution simulation method of 3-D TLC NAND flash memory.…”

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confidence: 94%

Modeling of program Vth distribution for 3-D TLC NAND flash memory

Wang

Lun

et al. 2019

Sci. China Inf. Sci.

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This paper proposes a simulation method to model the program Vth distribution of 3-D vertical channel TLC/QLC charge-trapping NAND flash memory. The program Vth distribution can be calculated by considering ISPP noise, WL-WL interference, and the RTN effect of tunneling oxide and poly Si, which are the major physical factors affecting the width of program Vth distribution. Then, the program Vth distribution shapes with different ISPP incremental voltage steps are compared, and the results are found to be consistent with the experimental results. Code and layer-dependent coupling coefficients of WL-WL interference in 3-D vertical channel NAND flash memory are considered. The effect of RTN on the program Vth distribution is comprehensively studied. The program Vth distribution of a WL is calibrated with the measurement, and a good agreement is obtained, validating the array program Vth distribution simulation method. The simulation method can help in improving the reliability of 3-D TLC NAND flash memory and provides guidance for the design and optimization of 3-D QLC NAND flash memory technology.

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Simulation on endurance characteristic of charge trapping memory

Cited by 7 publications

References 13 publications

Preparation of Remote Plasma Atomic Layer-Deposited HfO2 Thin Films with High Charge Trapping Densities and Their Application in Nonvolatile Memory Devices

Preparation of Remote Plasma Atomic Layer-Deposited HfO2 Thin Films with High Charge Trapping Densities and Their Application in Nonvolatile Memory Devices

Investigation of Retention Noise for 3-D TLC NAND Flash Memory

Modeling of program Vth distribution for 3-D TLC NAND flash memory

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