Simulation Study of Novel Trench Gate U-Shaped Channel SOI Lateral IGBTs With Suppressed Gate Voltage Overshoot and Reduced <i>di/dt</i>

Ma, Jun; Zhang, Long; Zhu, Jun‐Jie; Cui, Wangming; Sun, Weifeng; Huang, Feiming; Gu, Yu; Zhang, Sen; He, Nailong

doi:10.1109/ted.2021.3084578

Cited by 2 publications

(2 citation statements)

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“…1 (a)), and the displacement current composed of these holes can overcharge gate, resulting in high di/dt and gate overshoot (in Fig. 3 (a)) [7]. As shown in Fig.…”

Section: Structure and Mechanismmentioning

confidence: 94%

“…Recent years, many novel IGBTs with multiple ports or integrated devices have been reported to improve the carrier controllability in different transients. In the turn-on transient, better dv/dt or di/dt controllability can be achieved by controlling the hole concentration beside gate polysilicon [4], [5] or suppressing the effect of displacement current on gate voltage [6], [7]. In the turn-off transient, fast electron/hole extraction or decreasing stored carriers is crucial to achieve low turn-off loss (E OFF ).…”

Section: Introductionmentioning

confidence: 99%

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Four Hybrid Gates SOI Lateral Insulated Gate Bipolar Transistor With Improved Carrier Controllability

Pan

et al. 2023

IEEE J. Electron Devices Soc.

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Easy inter-connection is a crucial advantage of the single-chip power ICs, which makes power devices with multiple ports easy to improve carrier controllability without increasing process difficulty. Electrical characteristics of the power devices get further improved thanks to the advanced carrier controllability. In this paper, a silicon-on-isolator lateral IGBT (SOI-LIGBT) featured four hybrid gates is proposed to obtain outstanding carrier controllability in turn-on, turn-off and short-circuit conditions for the first time. Four hybrid gates include three planar gates (G 1 , G 2 and G 3 ) and a trench gate (G 4 ), of which G 3 and G 4 are grounded gate to lower saturation current and suppress latch up. Low turn-off time (t OFF ), di/dt and improved short-circuit withstanding capability are obtained through providing different input signals to these gates. In the turn-on, G 2 is pre-charged to a stable voltage equal to gate voltage (V G1 ) to suppress the high di/dt before V G1 starts to rise. In the turn-off, a P-type inversion is induced by the negative voltage of G 2 (V G2 ), which provides a low-resistance hole current path to extract the stored holes. In the short-circuit condition, G 3 and G 4 are both shorted to the ground to lower the saturation current and suppress the activation of parasitic NPN transistor, resulting in an improved short-circuit withstanding time (t SC ). Compared with the conventional SOI-LIGBT, t OFF and di/dt are reduced by 43.6% and 53.08%, and t SC is prolonged from 3.04µs to 8.89µs at DC bus voltage of 400V.INDEX TERMS Hybrid gates, carrier controllability, turn-on, di/dt, turn-off time, short-circuit, short-circuit withstanding time, SOI, lateral IGBT, LIGBT, SOI-LIGBT.

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“…1 (a)), and the displacement current composed of these holes can overcharge gate, resulting in high di/dt and gate overshoot (in Fig. 3 (a)) [7]. As shown in Fig.…”

Section: Structure and Mechanismmentioning

confidence: 94%