Simulations of Mask Error Enhancement Factor in 193 nm Immersion Lithography

Yeh, Kwei‐Tin; Loong, Wen−an

doi:10.1143/jjap.45.2481

Cited by 4 publications

(3 citation statements)

References 12 publications

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“…Generally speaking, image contrast 13,14 and the mask error enhancement factor 15 ͑MEEF͒ are used as the metrics to analyze the layout "quality." In this work, several throughpitch, line-to-tip, and tip-to-tip patterns are used for calculating the image contrast and the MEEF.…”

Section: Metricsmentioning

confidence: 99%

Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house’s approach

Wang

et al. 2007

J. Micro/Nanolith. MEMS MOEMS

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We describe design house approaches for design rule developments with emphasis of valuations of pre-optical proximity correction ͑pre-OPC͒ layouts and their simulation results. To begin, we describe the procedure of the simulation model calibration. An evaluation of metrics for analyzing the design layouts is then described. Due to the unavailability of post-OPC layouts, both pre-OPC and trial-OPC simulations are studied. A range of layout pattern density, within which the pre-OPC metric follows the post-OPC's, is estimated. Within this pattern density range, pre-OPC layout then can be evaluated to identify potential process "hot spots." With this approach, a set of design for manufacturability ͑DFM͒ compliance design rules is derived and applied to the product developments for both 90-and 65-nm process technology nodes. Several hot spots in the products ͑designed with 90-nm design rules͒ are located and fixed using layout optimization guided by the DFM rules. Simulated image contours and in-line scanning electron microscope ͑SEM͒ images validate the approach. © 2007 Society of Photo-Optical Instrumentation Engineers.

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Section: Metricsmentioning

confidence: 99%

Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house’s approach

Wang

et al. 2007

J. Micro/Nanolith. MEMS MOEMS

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“…Mask bias and attenuated background transmission have been widely studied in reticle optimization, with much effort devoted to the research of image log slope ͑ILS͒ and mask error enhancement factor ͑MEEF͒ through simulations, [8][9][10] theoretical approaches, 11,12 and matrix analysis. 13,14 While the capabilities of Hi-T reticle designs are clear, the concise form and explicit relations are rarely found in the literature.…”

Section: Introductionmentioning

confidence: 99%

Analytical optimization of high-transmission attenuated phase-shifting reticles

Yang

2009

J. Micro/Nanolith. MEMS MOEMS

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For sub-50-nm semiconductor patterning processes, extremely coherent illumination and high-transmission ͑Hi-T͒ attenuated background phase-shifting reticles are becoming increasingly important in delivering high-quality aerial images. Here, a Hi-T reticle is defined as any attenuated phase-shifting mask with a background transmission intensity of 12% or higher of incident light. While numerical simulation has served as a powerful tool in reticle design, the analytical relation of image log slope ͑ILS͒ and mask error enhancement factor ͑MEEF͒ are calculable in concise, exact form to reveal additional insight into reticle optimization. The properties of ILS and MEEF can be derived analytically in predicting the optimal range of mask bias in terms of image contrast and sensitivity for improved critical dimension ͑CD͒ control. These derived relations also demonstrate the capability for analysis beyond extensive numerical simulation and can be easily scaled and applied to various pitches and mask CDs. These relations are also verified in this paper with simulation of realistic process parameters and thus prove the applicability in optimization of Hi-T reticles.

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“…A normalized image log slope (NILS) has been used to evaluate the quality of pattern and susceptibility of the hotspot pattern to focus and exposure errors. The mask enhanced error factor (MEEF) for the dense pitch in general is higher than for isolated, and the higher MEEF causes lower NILS [11], [12] i.e., the lower the NILS in the dense pitch, the higher the probability of a bridging hotspot. As a result, the use of density filters may improve the detection accuracy of bridging hotspots.…”

mentioning

confidence: 99%

Fast Dual-Graph-Based Hotspot Filtering

Kahng

Park

2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-As advanced technologies in wafer manufacturing push patterning processes toward lower k 1 subwavelength printing, lithography for mass production potentially suffers from decreased patterning fidelity. This results in the generation of many hotspots, which are actual device patterns with relatively large critical-dimension and image errors with respect to on-wafer targets. Hotspots can be formed under a variety of conditions such as the original design being unfriendly to the resolution enhancement technique that is applied, unanticipated pattern combinations in rule-based optical proximity correction (OPC), or inaccuracies in model-based OPC. When these hotspots fall on locations that are critical to the electrical performance of a device, device performance and parametric yield can be significantly degraded. The golden verification signoff tool using a simulation-based approach has occupied the mainstream and has been able to accurately detect hotspots. However, this approach represents a runtime-quality tradeoff point that is high in quality but also high in runtime. There is also little point in trying to replace the golden signoff tool. We are motivated to develop a low-runtime "prefilter" that reduces the amount of layout area to be analyzed by the golden tool, without compromising the overall quality of hotspot finding. In this paper, we first describe a novel detection algorithm for hotspots induced by lithographic uncertainty. Our goal is to rapidly detect all lithographic hotspots without significant accuracy degradation. In other words, we propose a filtering method: as long as there are no "false negatives," i.e., we reliably obtain a superset of actual hotspots, then our method can dramatically reduce the layout area processed by golden hotspot analysis. Our hotspot detection algorithm includes layout graph construction, graph planarization, three-level bridging hotspot detection, and necking hotspot detection. We have tested our flow on several industry test cases. The experimental results show that our method is promising: for benchmark designs in 90-nm and 65-nm technologies, 100% of bridging and open hotspots are detected with few falsely detected hotspots. The average run- Manuscript received September 25, 2007; revised December 31, 2007 and March 13, 2008. Published August 20, 2008 time of our method is more than 496× faster compared to the commercial tool.

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Simulations of Mask Error Enhancement Factor in 193 nm Immersion Lithography

Cited by 4 publications

References 12 publications

Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house’s approach

Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house’s approach

Analytical optimization of high-transmission attenuated phase-shifting reticles

Fast Dual-Graph-Based Hotspot Filtering

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