Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264

Huang, K.; Han, Sang-Il; Popovici, K.; Brisolara, L.; Guérin, X.; Li, L.; Yan, Xinhai; Chae, Soo-Ik; Carro, Luigi; Jerraya, Ahmed

doi:10.1109/dac.2007.375049

Cited by 16 publications

(18 citation statements)

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“…16(c), Thread2 includes several Simulink blocks and links that will be transformed in the thread code. Figure 17 illustrates a multiprocessor platform that is automatically generated from the Simulink CAAM with hardware architecture generator [43]. It is a cycle-accurate SystemC model that consists of one ARM7 and two Xtensa CPU subsystems communicating through five GFIFO channels and two HWFIFO channels.…”

Section: Experiments With Motion-jpeg Decodermentioning

confidence: 99%

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Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC

Han

Chae²,

Brisolara³

et al. 2007

Des Autom Embed Syst

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Emerging embedded systems require heterogeneous multiprocessor SoC architectures that can satisfy both high-performance and programmability. However, as the complexity of embedded systems increases, software programming on an increasing number of multiprocessors faces several critical problems, such as multithreaded code generation, heterogeneous architecture adaptation, short design time, and low cost implementation. In this paper, we present a software code generation flow based on Simulink to address these problems. We propose a functional modeling style to capture data-intensive and controldependent target applications, and a system architecture modeling style to seamlessly transform the functional model into the target architecture. Both models are described using Simulink. From a system architecture Simulink model, a code generator produces a multithreaded code, inserting thread and communication primitives to abstract the heterogeneity of the target architecture. In addition, the multithread code generator called LESCEA applies the extensions of dataflow based memory optimization techniques, considering both data and control dependency. Experimental results on a Motion-JPEG decoder and an H.264 decoder show that the proposed multithread code generator enables easy software programming on different multiprocessor architectures with substantially reduced data memory size (up to 68.0%) and code memory size (up to 15.9%).

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Section: Experiments With Motion-jpeg Decodermentioning

confidence: 99%

“…To explore the design space of the H.264 decoder, we generated several multiprocessor platform models written in cycle-accurate SystemC with hardware architecture generator explained in [43] by increasing the number of Xtensa processors. GFIFO channels are used for inter-subsystem communications.…”

Section: Experiments With H264 Baseline Decodermentioning

confidence: 99%

Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC

Han

Chae²,

Brisolara³

et al. 2007

Des Autom Embed Syst

Self Cite

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“…For architectural exploration, the HLM is typically augmented with architecture information, i.e., number and type of processing and communication resources including buses and memories. By specifying the HLM mapping to this architecture, and by using estimates for execution times, so called Virtual Architecture Models can be generated, permitting a combined functional and timed simulation, and hence, an early performance estimation [2], [3]. After selecting the platform (i.e., an architecture instance) for implementation, the HLM can be reused in various scenarios: In hardware design, the HLM serves as golden model; in software design, parts of the executable HLM are integrated into a virtual prototype, allowing software development to start without the need for a hardware prototype.…”

Section: Introductionmentioning

confidence: 99%

Efficient High-Level modeling in the networking domain

Zebelein¹,

Falk²,

Haubelt³

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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-Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. However, writing good HLMs for complex systems is still a challenging task. In the context of network controller design, modeling complexity has two major sources: (1) the functionality to handle a single connection, and (2) the number of connections to be handled in parallel. In this paper, we will propose an efficient actor-oriented modeling approach for complex systems by (1) integrating hierarchical FSMs into dynamic dataflow models, and (2) providing new channel types to allow concurrent processing of multiple connections. We will show the applicability of our proposed modeling approach to real-world system designs by presenting results from modeling and simulating a network controller for the Parallel Sysplex architecture used in IBM System z mainframes.

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“…Hence, an oversimplified synthesis method might result in infeasible or suboptimal solutions only. Many approaches are heavily biased toward either computation synthesis (e.g., [15] and [16]) or communication synthesis (e.g., [17]- [19]), assuming the counterpart to be done by a different tool. In order to ensure feasibility and optimality, however, an ESL synthesis methodology should support computation and communication synthesis with all their respective subtasks.…”

Section: Esl Synthesismentioning

confidence: 99%

Electronic System-Level Synthesis Methodologies

Gerstlauer

Haubelt

Pimentel

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

140

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Abstract-With ever-increasing system complexities, all major semiconductor roadmaps have identified the need for moving to higher levels of abstraction in order to increase productivity in electronic system design. Most recently, many approaches and tools that claim to realize and support a design process at the so-called electronic system level (ESL) have emerged. However, faced with the vast complexity challenges, in most cases at best, only partial solutions are available. In this paper, we develop and propose a novel classification for ESL synthesis tools, and we will present six different academic approaches in this context. Based on these observations, we can identify such common principles and needs as they are leading toward and are ultimately required for a true ESL synthesis solution, covering the whole design process from specification to implementation for complete systems across hardware and software boundaries.

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Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264

Cited by 16 publications

References 0 publications

Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC

Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC

Efficient High-Level modeling in the networking domain

Electronic System-Level Synthesis Methodologies

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