Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC 2003
DOI: 10.1145/1119772.1119858
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Simultaneous floorplanning and buffer block planning

Abstract: Abstract-As technology advances and the number of interconnections among modules rapidly increases, timing closure and design convergence are the most important concerns. Hence, it is desirable to consider interconnect optimization as early as possible. In this paper, we first address simultaneous floorplanning and buffer block planning (i.e., integrating buffer block planning into floorplanning) for interconnect optimization. Experimental results show that our method can significantly improve the interconnect… Show more

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Cited by 11 publications
(9 citation statements)
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“…Deadspace means the interspace among the placed modules. Jiang et al [11] implemented floorplanning and buffer block planning simultaneously. In each iteration of SA, they constructed a routing tree for each net, allocated buffers, and introduced buffer blocks into the intermediate floorplan.…”
Section: Introductionmentioning
confidence: 99%
“…Deadspace means the interspace among the placed modules. Jiang et al [11] implemented floorplanning and buffer block planning simultaneously. In each iteration of SA, they constructed a routing tree for each net, allocated buffers, and introduced buffer blocks into the intermediate floorplan.…”
Section: Introductionmentioning
confidence: 99%
“…The UBF algorithm was implemented in the C++ language on a 450 MHz SUN Ultra 60 workstation and experimented on the six MCNC benchmark circuits used in [5,6,13,11]. See Table 2 for the statistics of the circuits.…”
Section: Resultsmentioning
confidence: 99%
“…The parameters for interconnects and buffers were based on the ¼ ½ Ñ technology given in the NTRS'97 roadmap [14] and were used in [5,6,11,13] (see Table 1 for the parameters). All parameters used are the same as [2,5,6,11].…”
Section: Resultsmentioning
confidence: 99%
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