Simultaneous hot-hole injection at drain and source for efficient erase and excellent endurance in SONOS flash EEPROM cells

Cho, Myung Kwan; Kim, D.M.

doi:10.1109/led.2003.810887

Cited by 12 publications

(1 citation statement)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Here, the programming was done by the source-side injection while the erase was done by conventional band-to-band hot hole erasing. The measured condition of the multi-level operation is programmed with V WL = 9 V, and V BL = 4 V for 10 µs, and erased with V WL = −4 V and V BL = 6 V for 5 ms. For the device with thick tunneling oxide (6 nm), however, the window is preserved but both values increase with repeated cycling, indicating incomplete erasure [31] or more interface state generation in the tunneling oxide. The thin bottom oxide exhibits better P/E cycling performance, resulting in the negligible V TH shift owing to the lower interface state generation (figure 8).…”

Section: Ono Thickness Optimization For the Wsg-sonos Memorymentioning

confidence: 98%

Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

Chao

Peng

et al. 2007

Semicond. Sci. Technol.

View full text Add to dashboard Cite

In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good V TH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 µs/5 ms) and low programming current (3.5 µA) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.

show abstract

Section: Ono Thickness Optimization For the Wsg-sonos Memorymentioning

confidence: 98%

Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

Chao

Peng

et al. 2007

Semicond. Sci. Technol.

View full text Add to dashboard Cite

show abstract

A charge pump without body effect that generates a positive or negative high voltage

Yamazoe

Yamasaki

Oodaira

et al. 2005

Electron. Comm. Jpn. Pt. II

View full text Add to dashboard Cite

SUMMARYWe propose a new high-efficiency CMOS charge pump circuit that generates a high positive or negative voltage by using a low operating voltage of 1.5 V. By controlling the body voltage and boosting the gate voltage of the nMOSFET, the back bias effect is removed and the voltage gain per unit stage is not affected by the threshold voltage. The proposed circuit can output a high voltage of 10 V when a 0.18-µm CMOS processing chip that operates at a voltage as low as 1.5 V is used. Furthermore, by replacing the input and output the circuit can generate a high positive or negative voltage. In addition, we demonstrate that a different positive voltage and current are output at the same time by a series connection to this charge pump.

show abstract

Potentiality of healing techniques in hot-carrier damaged 28 nm FDSOI CMOS nodes

Bravaix

Cacho

Federspiel

et al. 2016

Microelectronics Reliability

View full text Add to dashboard Cite

Simultaneous hot-hole injection at drain and source for efficient erase and excellent endurance in SONOS flash EEPROM cells

Cited by 12 publications

References 6 publications

Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

A charge pump without body effect that generates a positive or negative high voltage

Potentiality of healing techniques in hot-carrier damaged 28 nm FDSOI CMOS nodes

Contact Info

Product

Resources

About