Simultaneous Multi-channel Data Acquisition and Storing System

Abdallah, Mouin; Elkeelany, Omar

doi:10.1109/icc.2009.17

Cited by 8 publications

(11 citation statements)

References 5 publications

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“…In another work, Abdallah and Elkeelany [15] proposed a FPGA-based simultaneous multi-channel data acquisition system and they had verified the proposed architecture for analog signals. The design includes analog-to-digital converter to convert the analog signal to digital data.…”

Section: Review Of the Related Workmentioning

confidence: 99%

“…FPGAs have been used for prototype design in a range of engineering application [1,[14][15][16][17][18][19]; however, till date to the authors' knowledge, the design of a complete application-specific controller for different flash memory card access with detailed description of the modules and their operation is limited. Table 1 depicts some of the earlier work in this domain.…”

Section: Review Of the Related Workmentioning

confidence: 99%

“…Some researchers [15][16][17][18] have taken help of highlevel languages or external controllers, on-board processors, and other resources apart from only FPGA logic resources during implementation of data access mechanism. In some paper [14,15,23,29,30], partially, FSM-based approaches have been used for realization of data transfer mechanism. The single/multiple blocks read/write procedures were designed using FSM, and they have been implemented those procedures using HDL for target device.…”

Section: Review Of the Related Workmentioning

confidence: 99%

“…Another work was proposed in the literature where the SDHC card had been used in SD mode (i.e., bulk data transfer mode) for video signal storage and processing [14]. With the newly emerging technologies, flash-based memory devices have been used as the efficient storage unit and till now it accomplishes the need of memory storage even on the modern era of technological advancement [2,3,[15][16][17][18][19][20][21][22][23].…”

Section: Introductionmentioning

confidence: 99%

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A low cost and fast controller architecture for multimedia data storage and retrieval to flash-based storage device

Banerjee

Mukhopadhyay

2016

J Embedded Systems

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Real-time multimedia data access plays an important role in electronic systems; as time goes by, with decrease in data processing speed and increase in communication time, storage time, and retrieval time, the overall response time increases for real-time applications. Therefore, in this paper, a novel real-time, fast, low-cost, system-on-chip (SoC) controller has been proposed and implemented where large volume of data can be efficiently stored and retrieved from flash memory cards. It is being implemented only using hardware description language (HDL) on a field programmable gate array (FPGA) chip without using any other on-board or external hardware resources or high-level languages. The entire controller architecture, in a single chip, contains five different modules and is designed using finite state machine (FSM)-based approach. The modules are card initialization module (CINM), idle module (IM), card read module (CRM), card write module (CWM), and decision module (DM). The architecture is completely synthesized for Spartan 3E xc3s500e-4-fg320 FPGA with only 5% of the total logic utilization. The experimental results tested for microSD, SD, and SDHC cards of different size, and these show that the architecture uses less hardware and clock cycles for card initialization and single/multiblock read/write procedure.

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Section: Review Of the Related Workmentioning

confidence: 99%

Section: Review Of the Related Workmentioning

confidence: 99%

Section: Review Of the Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A low cost and fast controller architecture for multimedia data storage and retrieval to flash-based storage device

Banerjee

Mukhopadhyay

2016

J Embedded Systems

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“…Also, the maximum speed which the standard supports increased to 12.5Gbps. [2] Before JESD204B, there were already several published and implemented designs [3] - [11] to interface a converter with an ASIC or FPGA chip. For instance, in the paper of Mahat et.…”

Section: Introductionmentioning

confidence: 99%

Development of Framer/Deframer for 5Gbps JESD204B Soft IP

Escabal¹,

Raffiñan²,

Hora³

2018

IJET

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This paper aimed to modify and redesign theJESD204B Full System of Lattice Semiconductor, particularly the TX deframer and RX framer modules used for the 3Gbps JESD204B soft IP to support the recently released 5Gbps JESD204B Soft IP. The modified full system instantiating the new 5Gbps JESD204B Soft IP had to be tested for functionality through RTL and gate simulation and tested for timing through Static Timing Analysis. The transaction layer's RX framer, TX deframer, and the clock generator modules were identified to be the major blocks of the full system affected by the change in the soft IP. These were redesigned, followed by RTL and gate simulation of the full system. STA was checked through the Lattice Diamond tool. The system passed the simulation tests. Also, STA results showed that timing was still relaxed even if the lane speed was increased, ensuring that timing requirements are achieved by the device. It is recommended that the full system's other blocks, and the testbench for the JESD204B and other soft IP products be investigated to operate at a higher clock frequency without violating the timing requirements and constraints of the ECP5 device.

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A comprehensive embedded solution for data acquisition and communication using FPGA

Venkatraman

Moorthi

Selvan

et al. 2017

Journal of Applied Research and Technology

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Digital controllers in real time applications require a reliable system for acquisition of data for effective processing. This paper focusses on the design and development of a comprehensive embedded solution for data acquisition and communication using field programmable gate array (FPGA). In the proposed solution, an embedded platform is developed which acquires the data, monitors and provides essential communication between the devices connected via Ethernet in a network. The system utilizes server/client architecture mode of communication; control signals for the appliances connected to the client are controlled by the server and the status of appliances are displayed at server end for online monitoring. The proposed embedded solution works without a dedicated personal computer. The versatility and efficacy of the proposed platform is tested experimentally by employing it in a prototype of laboratory built micro-grid.

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Simultaneous Multi-channel Data Acquisition and Storing System

Cited by 8 publications

References 5 publications

A low cost and fast controller architecture for multimedia data storage and retrieval to flash-based storage device

A low cost and fast controller architecture for multimedia data storage and retrieval to flash-based storage device

Development of Framer/Deframer for 5Gbps JESD204B Soft IP

A comprehensive embedded solution for data acquisition and communication using FPGA

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