2024
DOI: 10.21203/rs.3.rs-4102834/v1
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Simultaneous Optimization of Network-on-Chip for Improved Reliability and Reduced Average Packet Latency Considering Buffer Size Constraints

Hesam Abdolhosseini,
Hamid R. Zarandi

Abstract: Managing the complex interconnections found in contemporary chip designs is achievable through the utilization of network-on-chip (NoC) architectures. Optimizing NoC configuration is critical for balancing reliability and latency. This paper presents a study on simultaneously optimizing NoC to improve reliability and reduce average packet latency, while considering buffer size constraints. Buffer size significantly impacts latency, cost, and reliability, making it a key element for optimization. To validate la… Show more

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