Simultaneous reduction in volume of test data andpowerdissipation for systems-on-a-chip

Rosinger, P.; Gonciari, P.T.; Al-Hashimi, B.M.; Nicolici, Nicola

doi:10.1049/el:20010981

Cited by 41 publications

(25 citation statements)

References 2 publications

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“…The methods about low power mapping and test compression for unspecified scan vectors were proposed [4,5]. Also, a new compression and low power consumption technique using Scan Latch Reordering(SLR) was proposed [6,7]. It mapped the don't care input for low power and performed the SLR [8].…”

Section: Introductionmentioning

confidence: 99%

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Low Power Test for SoC(System-On-Chip)

Jung¹

2011

Journal of information and communication convergence engineerin

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Section: Introductionmentioning

confidence: 99%

“…Also, a new compression and low power consumption technique using Scan Latch Reordering(SLR) was proposed [6,7]. It mapped the don't care input for low power and performed the SLR [8].…”

Section: Introductionmentioning

confidence: 99%

Low Power Test for SoC(System-On-Chip)

Jung¹

2011

Journal of information and communication convergence engineerin

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“…Test vector ordering [27], gated clock scheme [28], scan latch partitioning [29], test generation for low power scan testing [30], static compression to reduce power [2], mixed compression/decompression and low power test application techniques based on Golomb codes [31], FDR codes [11] and MTC [12] [13] are among the proposed techniques.…”

Section: Introductionmentioning

confidence: 99%

RL-huffman encoding for test compression and power reduction in scan applications

Nourani

Tehranipour

2005

ACM Trans. Des. Autom. Electron. Syst.

116

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Abstract-This paper mixes two encoding techniques to reduce test data volume, test pattern delivery time and power dissipation in scan test applications. This is achieved by using Run-Length encoding followed by Huffman encoding. This combination is especially effective when the percentage of don't cares in a test set is high which is a common case in today's large SoCs. Our analysis and experimental results confirm that achieving up to 89% compression ratio and 93% scan-in power reduction is possible for scan testable circuits such as ISCAS89 benchmarks.

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“…Comparing the 9C technique with the other techniques (FDR [10], VIHC [13], MTC [12] and Selective Huffman [7]) is shown in Table IV. As the last row shows the average compression ratio of the 9C technique is more than others.…”

Section: Resultsmentioning

confidence: 99%

“…Compression methods such as statistical coding [5] [6], selective Huffman coding [7], Golomb coding [8], FDR coding [9], alternating run-length coding using FDR [10], EFDR coding [11], MTC coding [12] and VIHC coding [13] have been proposed to reduce test data volume. These techniques compress T D without requiring any structural information for the test application from the core vendor.…”

Section: Introductionmentioning

confidence: 99%

Nine-coded compression technique with application to reduced pin-count testing and flexible on-chip decompression

Tehranipour¹,

Nourani²,

Chakrabarty³

Proceedings Design, Automation and Test in Europe Conference and Exhibition

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Abstract-This paper presents a new test data compression technique based on a compression code that uses exactly nine codewords. In spite of its simplicity, it provides significant reduction in test data volume and test application time. In addition, the decompression logic is very small and independent of the precomputed test data set. Our technique leaves many don't-care bits unchanged in the compressed test set, and these bits can be filled randomly to detect non-modeled faults. The proposed technique can be efficiently adopted for single-or multiple-scan chain designs to reduce test application time and pin requirement. Experimental results for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique.

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Simultaneous reduction in volume of test data andpowerdissipation for systems-on-a-chip

Cited by 41 publications

References 2 publications

Low Power Test for SoC(System-On-Chip)

Low Power Test for SoC(System-On-Chip)

RL-huffman encoding for test compression and power reduction in scan applications

Nine-coded compression technique with application to reduced pin-count testing and flexible on-chip decompression

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