Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture

Abstract

Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based resource binding approach based on a distributed register-file microarchitecture (DRFM), which makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. DRFM contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. Compared to the traditional discrete-register counterpart, a DRFM allows use of the platformfeatured on-chip memory or register-file IP blocks to implement its local register files, and this results in a substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing inter-island connections for synthesis algorithms. Given the scheduling solution and resource (functional units) constraints, two novel algorithms in the resource binding stage are developed based on DRFM: (i) A simultaneous DRFM clustering and binding algorithm, which decides the configuration of DRFM and the assignment of operations into islands with the focus on optimizing global connections; (ii) A data-forwarding scheduling algorithm, which takes advantage of the operation slacks to handle the read-port restriction of register files. On the Xilinx Virtex4 FPGA platform, experimental results with a set of real-life test cases show a 50% logic area reduction achieved by applying our approach, with a 14.6% performance improvement, compared to the traditional discrete-register-based approach. Also, experiments on small-size designs show that our algorithm produces the same number of total connections and at most one more maximum feeding-in connection compared to optimal solutions generated by ILP.

Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay

“…3(a), those two IITs merely need one IIC (i.e., from I B to I A ). As previously mentioned, in DRFM, the number of IICs has been proven to be an appropriate metric to evaluate the quality of result in terms of both cycle time and area at early design phases [14], [15]. Hence, if minimizing global interconnect resource is the primary goal, the main concern of synthesis flows targeting DRFM is to reduce the number of IICs instead of IITs.…”

“…As in [14], [15], it is commonly assumed that every operation can be carried out at arbitrary island. Then the problem formulation of this work can be described as: Given a DFG and a resource constraint (the number of available islands), obtain a scheduled and bound DFG with minimized latency targeting DRFM-IID.…”

“…The distributed register-file microarchitecture (DRFM) is one of the DR-based architectures and is recently proposed in [14], [15]. As shown in Fig.…”

“…In DRFM, the notion of inter-island connections (IICs) is presented to better estimate the actual cost of physical global interconnects. Hence, the number of IICs is usually considered as a metric for quality of result (QoR) at early design phases [14], [15]. Meanwhile, unlike IICs, interisland transfers (IITs) are the actual data transfers taking place.…”

SUCA: a scalable unicore architecture with novel instruction encoding and distributed execution control

“…Clustered architectures [2,3,4,5] have been proposed to improve the scalability and performance by partitioning resources in critical timing paths like register files among clusters. However, the scalability achieved this way is still limited by traditional instruction encoding and centralized instruction execution control.…”