Simultaneous Timing Driven Clustering and Placement for FPGAs

Abstract

Abstract. Traditional placement algorithms for FPGAs are normally carried out on a fixed clustering solution of a circuit. The impact of clustering on wirelength and delay of the placement solutions is not well quantified. In this paper, we present an algorithm named SCPlace that performs simultaneous clustering and placement to minimize both the total wirelength and longest path delay. We also incorporate a recently proposed path counting-based net weighting scheme [16]. Our algorithm SCPlace consistently outperforms the state-of-the-art FPGA placement flow (T-VPack + VPR) with an average reduction of up to 36% in total wirelength and 31% in longest path delay.

Simultaneous timing-driven placement and duplication

“…We implemented our SPD algorithm under the framework of our previous work SCPlace [3]. For the purpose of comparison, we downloaded the VPR 4.3 source code, architecture file and the complete set of 20 MCNC benchmark circuits used by VPR from [14].…”

“…Since SPD explores different clustering solutions via duplication during the placement, it is natural to compare with our recent work SCPlace [3], which performs simultaneous clustering and placement optimization. Without the path counting-based net weighting scheme, SPD-m outperforms SCPlace by a few percentages; with path counting, both SPD-m and SCPlace achieve similar improvement of around 26%; when all three techniques are combined, we outperform T-Vpack + VPR by 31%.…”

Efficient and Deterministic Parallel Placement for FPGAs

“…In addition, Q2P is able to decompose its logic clusters back into their component LUTs and registers late in the placement process, allowing for "fine-tuning" of the placement details. This technique first appeared in Timberwolf [Sun and Sechen 1995] and has also been proposed as an extension to VPR [Chen and Cong 2004]. This results in a substantial improvement in various quality metrics, but since it greatly increases the effective size of the placement problem, it comes at a significant runtime cost.…”

Timing-Driven Nonuniform Depopulation-Based Clustering

“…Power-driven Timing-driven Routability-driven P-T-VPack, [18] SMAC, [12] SCPlace, [10] T-VPack, [4] T-RPack, [9] HDPack, [13] Marrakchi et al [11] * Target less than max logic utilization: "depopulated" CLBs Uniform depopulation * Non-uniform depopulation * T-NDPack Un/DoPack, [3] Tom and Lemieux [7] iRac, [5] Tessier and Giza [6] Figure 1: Categorization of clustering techniques based on logic utilization approach and optimization goals.…”

“…Therefore if few available BLEs are left in a CLB and related block is not available, it is wiser to leave the BLEs unused. Typically, clustering techniques modify the cost function ( [4,5,9]) or the algorithm flow [10] or both ( [11][12][13]). Here we summarize in what capacity the well-known approaches enhance the clustering flow and highlight where our approach stands relative to them.…”