Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

Yang, Yong Sook; Jeong, Hong; Song, Seung Chul; Wang, Joseph; Yeap, Geoffrey; Jung, Seong‐Ook

doi:10.1109/tcsi.2016.2556118

Cited by 32 publications

(21 citation statements)

References 19 publications

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“…Budhaditya et al, [4] implemented a single bit line 6T SRAM cell, where there is high delay due to which the performance of read and write operations are severely degraded. Yang et al, [5] implemented 7T SRAM cell in Fin FET technology, but the power consumption is high. For low power applications Ansari et al, [6] designed a 7T SRAM cell, but didn't calculate power and overall delay.…”

Section: Literature Reviewmentioning

confidence: 99%

Low voltage high speed 8T SRAM cell for ultra-low power applications

Kumar¹,

Satyanarayana²

2018

IJET

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The usage of portable devices increasing rapidly in the modern life has led us to focus our attention to increase the performance of the SRAM circuits, especially for low power applications. Basically in six-Transistor (6T) SRAM cell either read or write operation can be performed at a time whereas, in 7T SRAM cell using single ended write operation and single ended read operation both write and read operations will be accomplished simultaneously at a time respectively. When it comes to operate in sub threshold region, single ended read operation will be degraded severely and single ended write operation will be severely degraded in terms of write-ability at lower voltages. To encounter these complications, an eight transistor SRAM cell is proposed. It performs single ended read operation and single ended write operation together even at sub threshold region down to 0.1V with improved read-ability using read assist and improved dynamic write-ability which helps in reducing the consumption of power by attaining a lower data retention voltage point. To reduce the total power consumption in the circuits, two extra access transistors are used in 8T SRAM cell which also helps in reducing the overall delay.

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Section: Literature Reviewmentioning

confidence: 99%

Low voltage high speed 8T SRAM cell for ultra-low power applications

Kumar¹,

Satyanarayana²

2018

IJET

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“…To reduce the threshold variations in bulk-CMOS, FinFETs are extensively used in sub nanometer technologies to reduce the threshold variations in bulk-CMOS [21,22]. The main advantage of FinFET device is that it reduces the random dopant fluctuation (RDF), which is the key reason behind the threshold voltage variations in ultra-low voltage (ULV) operations.…”

Section: Comparison To Finfet-based Srammentioning

confidence: 99%

“…Additionally, it is not easy to improve read and write stability in ULV operations. In addition, for more analysis of FinFET based SRAM, Younghwi et al [22] presented FinFET C6T, RD8T, and ST10T SRAM architectures in 14 nm Technology. The results in Table 4 show that FinFET-based SRAM design has very high read and write access speed as compared to the proposed bulk CMOS-based PT10T SRAM.…”

Section: Comparison To Finfet-based Srammentioning

confidence: 99%

Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Singh

Vishvakarma

2017

JLPEA

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Abstract:In this paper, an ultra-low power (ULP) 10T static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates at sub-threshold voltage. The proposed SRAM has the tendency to operate at low supply voltages with high static and dynamic noise margins. The IoT application requires battery-enabled low leakage memory architecture in a subthreshold regime. Therefore, to improve leakage power consumption and provide better cell stability, a power-gated robust 10T SRAM is presented in this paper. The proposed cell uses a power-gated p-MOS transistor to reduce the leakage power or static power in standby mode. Moreover, due to the stacking of n-MOS transistors in 10T SRAM latch and by separating the read path from the 10T SRAM latch, the static and dynamic noise margins in read and write operations has shown significant tolerance w.r.t. the variations in device process, voltage, and temperature (PVT) values. The proposed SRAM shows significantly improved performance in terms of leakage power, read static noise margin (RSNM), write static noise margin (WSNM), write ability or write trip point (WTP), read-write energy, and dynamic read margin (DRM). Furthermore, these parameters of the proposed cell are observed at 8-Kilo bit (Kb) SRAM and compared with existing SRAM architectures. From the Monte Carlo simulation results, it is observed that the leakage power of a proposed low threshold voltage-LVT 10T SRAM is reduced by 98.76%, 98.6%, 6.7%, and 98.2% as compared to the LVT C6T, RD8T, LP9T, and ST10T SRAM, respectively, at 0.3V VDD. Additionally, in the proposed 10T SRAM, parameters such as RSNM, WSNM, WTP, and DRM are improved by 3×, 2×, 1.11×, and 1.32×, respectively, as compared to C6T SRAM. Similarly, the proposed 10T SRAM shows an improvement of 1.48×, 1.25×, and 1.1× in RSNM, WSNM, and WTP, respectively, in the parameters as compared to RD8T SRAM at 0.3 V VDD.

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“…SRAM technology is more suitable for high-speed and low-power applications like processors, computing units and other sophisticated devices, scientific and industrial subsystems, modern appliances, automotive electronics, mobile phones etc [1], [2]. Low-Power, Low-Voltage stability with high packaging density has represented the fundamental topics of the recent decade regarding SRAM outlines [3]. The reduction of the supply voltage offers the greatest energy efficiency since the dynamic power has been quadratic function of voltage [4].…”

Section: Introductionmentioning

confidence: 99%

“…The past industry evolved patterns to investigate the bigger cell and more colorful SRAM hardware styles are in the scaled environments [7]. Some of the existing architectures of SRAM cell are 6T, 7T, 8T, 9T, 10T [1], [3], 11T [5] and 13T [6]. The 6T-SRAM cell suffers from read/write access distribution, scaling, soft errors and stability of the cell diminishes at low-voltage.…”

Section: Introductionmentioning

confidence: 99%

Energy optimization of 6T SRAM cell using low-voltage and high-performance inverter structures

Reddy¹,

Sailaja²,

Babulu³

2019

IJECE

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The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.

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Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

Cited by 32 publications

References 19 publications

Low voltage high speed 8T SRAM cell for ultra-low power applications

Low voltage high speed 8T SRAM cell for ultra-low power applications

Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Energy optimization of 6T SRAM cell using low-voltage and high-performance inverter structures

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